Semiconductor device including a superlattice and replacement metal gate structure and related methods

• US 10,084,045 B2
• Filed: 06/27/2017
• Issued: 09/25/2018
• Est. Priority Date: 11/25/2014
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Mears, Robert J., King Liu, Tsu-Jae, Takeuchi, Hideki
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US15/633,918
• Publication Number:
  US 20170301757A1
• Time in Patent Office: 455 Days
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/154 comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET

Abstract

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Claims

1. A semiconductor device comprising:

a substrate having a channel recess therein;

a plurality of spaced apart shallow trench isolation (STI) regions in said substrate;

source and drain regions spaced apart in the substrate and between a pair of the STI regions; and

a superlattice channel in the channel recess of said substrate extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and

a replacement gate over the superlattice channel having lateral edges vertically aligned with lateral edges of the superlattice channel.

2. The semiconductor device of claim 1 further comprising a well implant in the substrate between the pair of STI regions.

3. The semiconductor device of claim 1 wherein the replacement gate comprises:

a high K dielectric layer over the superlattice channel; and

a metal gate electrode over the high K dielectric layer.

4. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

5. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

6. The semiconductor device of claim 1 wherein the at least one non-semiconductor layer comprises oxygen.

7. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

8. The semiconductor device of claim 1 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

9. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.

10. A semiconductor device comprising:

a substrate having a channel recess therein;

a plurality of spaced apart shallow trench isolation (STI) regions in said substrate;

source and drain regions spaced apart in the substrate and between a pair of the STI regions;

a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and

a replacement gate comprising a high K dielectric layer over the superlattice channel and a metal gate electrode over the high K dielectric layer, the replacement gate having lateral edges vertically aligned with lateral edges of the superlattice channel.

11. The semiconductor device of claim 10 further comprising a well implant in the substrate between the pair of STI regions.

12. The semiconductor device of claim 10 wherein the superlattice channel further comprises a base silicon cap layer on an uppermost group of layers.

13. The semiconductor device of claim 10 wherein at least some semiconductor atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

14. A semiconductor device comprising:

a substrate;

a pair of spaced apart isolation regions in said substrate;

source and drain regions spaced apart in the substrate and between the pair of the isolation regions;

the substrate having a channel recess extending between the source and drain regions;

a superlattice channel in the channel recess and contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and

a gate over the superlattice channel comprising a dielectric layer and a metal gate electrode thereon, the gate having lateral edges vertically aligned with lateral edges of the superlattice channel.

15. The semiconductor device of claim 14 further comprising a well implant in the substrate between the pair of isolation regions.

16. The semiconductor device of claim 14 wherein the dielectric layer comprises a high K dielectric layer.

17. The semiconductor device of claim 14 wherein each base semiconductor portion comprises silicon.

18. The semiconductor device of claim 14 wherein each base semiconductor portion comprises germanium.

19. The semiconductor device of claim 14 wherein the at least one non-semiconductor layer comprises oxygen.

20. The semiconductor device of claim 14 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

21. The semiconductor device of claim 14 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

22. The semiconductor device of claim 14 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.