Memory devices for pattern matching

• US 10,089,359 B2
• Filed: 09/01/2016
• Issued: 10/02/2018
• Est. Priority Date: 04/18/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: De Santis, Luca, Marotta, Giulio G., Tiburzi, Marco-Domenico, Vali, Tommaso, Roohparvar, Frankie F., Macerola, Agostino
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Rankin, Candice A
• Application Number:
  US15/253,965
• Publication Number:
  US 20160371335A1
• Time in Patent Office: 761 Days
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 16/24558 Binary matching operations
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 7/20 Comparing separate sets of record carriers arranged in the same sequence to determine whether at least some of the data in one set is identical with that in the other set or sets
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Claims

1. A memory device, comprising:

an array of memory cells;

a controller;

a plurality of key registers to store a representation of a key word to be searched; and

a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells;

wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries;

wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells;

wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; and

wherein the memory device is further configured to determine an error count by;

precharging a selected data line of a string of memory cells of the array of memory cells;

sensing on the selected data line;

if the selected data line does not discharge, storing an error count value of zero;

if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges;

if the data line does not discharge, storing an error count value equal to the reference current level; and

if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and

storing an error count based on the reference current at which the data line remains charged.

2. The memory device of claim 1, wherein the memory device is further configured to compare selected programmed bits of the key word to data stored in the array of memory cells.

3. The memory device of claim 1, wherein each bit of the key word is programmed into two bits of a respected one of the plurality of key registers that correspond to gate voltages to be applied to gates of two respective memory cells of the stored data.

4. The memory device of claim 3, wherein the memory device is further configured to apply the programmed gate voltages of a selected bit of the key word to be searched to control gates of the two respective memory cells of the stored data.

5. The memory device of claim 1, wherein the memory device is further configured to indicate a match when a precharged data line connected to a string of memory cells containing the two respective memory cells does not discharge on sensing.

6. The memory device of claim 1, wherein the memory device is further configured to indicate a non-match when a precharged data line connected to a string of memory cells containing the memory cells discharges on sensing.

7. A memory device, comprising:

an array of memory cells;

a controller;

a plurality of key registers to store a representation of a key word to be searched; and

a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit of the key word from a key register of the plurality of key registers to compare to data stored in the array of memory cells;

wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries;

wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells;

wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; and

wherein each multiplexer of the plurality of multiplexers is configured to;

receive a plurality of voltage levels;

apply a first voltage level of the plurality of voltage levels to one access line of a corresponding string of memory cells of the array of memory cells when the bit of the key word has a first value;

apply a second voltage level of the plurality of voltage levels to the one access line of the corresponding string of memory cells when the bit of the key word has a second value different than the first value;

apply the second voltage level to an other access line of the corresponding string of memory cells when the bit of the key word has the first value;

apply the first voltage level to the other access line of the corresponding string of memory cells when the bit of the key word has the second value; and

apply a particular voltage level of the plurality of voltage levels to remaining access lines of the corresponding string of memory cells regardless of the value of the bit of the key word; and

wherein the memory device is further configured to determine an error count by;

precharging a selected data line of a string of memory cells of the array of memory cells;

sensing on the selected data line;

if the selected data line does not discharge, storing an error count value of zero;

if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges;

if the data line does not discharge, storing an error count value equal to the reference current level; and

if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and

storing an error count based on the reference current at which the data line remains charged.

8. The memory device of claim 7, wherein each access line of the corresponding string of memory cells is coupled to a control gate of a memory cell of the corresponding string of memory cells.

9. The memory device of claim 8, wherein the particular voltage level is configured to activate a memory cell of the corresponding string of memory cells regardless of a data value of that memory cell.

10. The memory device of claim 7, wherein each multiplexer of the plurality of multiplexers is configured to receive the same plurality of voltage levels.

11. The memory device of claim 7, wherein the particular voltage level is selected from a group consisting of the first voltage level and the second voltage level.

12. A memory device, comprising:

an array of memory cells;

a controller;

a plurality of key registers to store a representation of a key word to be searched; and

a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit of the key word from a corresponding key register of the plurality of key registers to compare to data stored in the array of memory cells;

wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries;

wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells;

wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells;

wherein each multiplexer of the plurality of multiplexers is configured to apply respective voltage levels to a plurality of access lines of a corresponding string of memory cells of the array of memory cells in response to its selected representation of a bit of the key word; and

wherein the memory device is further configured to determine an error count by;

precharging a selected data line of a string of memory cells of the array of memory cells;

sensing on the selected data line;

if the selected data line does not discharge, storing an error count value of zero;

if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges;

if the data line does not discharge, storing an error count value equal to the reference current level; and

if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and

storing an error count based on the reference current at which the data line remains charged.

13. The memory device of claim 12, further comprising:

wherein each key register of the plurality of key registers comprises a number of bit positions; and

wherein the memory device is configured to store a representation of each bit of the key word into a pair of bit positions of a corresponding key register of the plurality of key registers.

14. The memory device of claim 13, wherein each multiplexer of the plurality of multiplexers, in response to a select signal having a particular value, is configured to select a particular pair of bit positions of its corresponding key register.

15. The memory device of claim 14, wherein each pair of bit positions of each key register of the plurality of key registers is selectable in response to a respective value of the select signal.

16. The memory device of claim 14, wherein each multiplexer of the plurality of multiplexers is configured to apply respective voltage levels to a pair of access lines of the plurality of access lines of its corresponding string of memory cells having voltage levels corresponding to values of the particular pair of bit positons of its corresponding key register, and to apply a particular voltage level to remaining access lines of the plurality of access lines regardless of the values of the particular pair of bit positons of its corresponding key register.