Apparatus for testing electronic devices

• US 10,094,872 B2
• Filed: 03/03/2016
• Issued: 10/09/2018
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: AEHR Test Systems
• Original Assignee: AEHR Test Systems
• Inventors: Richmond, II, Donald P., Deboe, Kenneth W., Uher, Frank O., Jovanovic, Jovan, Lindsey, Scott E., Maenner, Thomas T., Shepherd, Patrick M., Tyson, Jeffrey L., Carbone, Mark C., Burke, Paul W., Cao, Doan D., Tomic, James F., Vu, Long V.
• Primary Examiner(s): Duverne, Jean F
• Application Number:
  US15/060,443
• Publication Number:
  US 20160187416A1
• Time in Patent Office: 950 Days
• CPC Class Codes: G01R 31/003 Environmental or reliability tests of individual semiconductors G01R31/2642; of PCB's G01R31/2817; of IC's G01R31/2855; of other circuits G01R31/2849
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/2642 Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2868 Complete testing stations; systems; procedures; software aspects
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2872 related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
• CPC Class Codes: G01R 31/2877 related to cooling
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G06F 8/30 Creation or generation of source code

Abstract

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Claims

1. A software assembly and test method, comprising:

storing a plurality of net files, each net file having information representing a scheme of current passing through conductors of a respective electrical subassembly;

providing an input of an interconnection scheme of a plurality of the electrical subassemblies connected to one another; and

assembling a plurality of the net files based on the interconnection scheme to construct a configuration file having information representing flow of current through the electrical subassemblies of the interconnection scheme;

connecting an electronic device through the electrical sub assemblies of the interconnection scheme to a test head; and

executing a test application, the test application utilizing a test program and the configuration file to provide instructions to the electrical sub assemblies of the interconnection scheme with the configuration file determining flow of current between the test head and the electronic device through the electrical sub assemblies of the interconnection scheme to test the electronic device.

2. The method of claim 1, wherein the input is provided manually.

3. The method of claim 1, wherein the electrical subassemblies include pattern generator, driver, and power boards.

4. The method of claim 3, wherein the electrical subassemblies include a plurality of pattern generator, driver, and power boards divided into physical zones with each physical zone including one pattern generator board, at least one driver board, and at least one power board connected to one another.

5. The method of claim 4, wherein the configuration file has a zone name field indicating a plurality of respective ones of the physical zones.

6. The method of claim 5, wherein physical zones having the same zone name field are grouped into a logical zone.

7. The method of claim 6, wherein the electrical subassemblies in the logical zone are of the same type and run the same test program at the same time.

8. The method of claim 1, wherein the configuration file has channel number and pad label fields to represent a relationship between channels and contacts of a plurality of devices.

9. The method of claim 8, wherein the interconnection scheme has a line connected to a set of the devices and a plurality of respective select lines connected to respective ones of the devices of the set, further comprising using the net files to construct a shared resources map representing a relationship between the select lines and the devices of the set.

10. The method of claim 9, wherein the select lines are grouped into chip select states.

11. The method of claim 1, further comprising transferring the configuration file to a tester apparatus, the tester apparatus including the electrical subassemblies.

12. A software assembler application and tester, comprising:

a plurality of net files, each file having information representing a scheme of current passing through conductors of a respective electrical sub assembly;

an input module to provide an input of an interconnection scheme of a plurality of electrical sub assemblies; and

an assembly module that assembles a plurality of the net files based on the interconnection scheme and constructs a configuration file having information representing flow of current through the electrical sub assemblies of the interconnection scheme;

a test head;

a holder for an electronic device, the electronic device being connected through the electrical sub assemblies of the interconnection scheme to the test head;

a test program; and

a test application, the test application utilizing a test program and the configuration file to provide instructions to the electrical sub assemblies of the interconnection scheme with the configuration file determining flow of current between the test head and the electronic device through the electrical sub assemblies of the interconnection scheme to test the electronic device.

13. The software assembler application of claim 12, wherein the input module includes an interface with a list of selectable inputs.

14. The software assembler application of claim 13, wherein the interface allows an operator to select the input of the interconnection scheme.

15. The software assembler application of claim 12, wherein the electrical subassemblies are selected from one or more of the group consisting of a pattern generator board, driver board and a power board.

16. The software assembler application of claim 12, wherein the input includes how the electrical subassemblies are to be connected to one another.