Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance

• US 10,096,540 B2
• Filed: 05/13/2011
• Issued: 10/09/2018
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Lee, KyungHoon, Park, SeongWon, Jang, KiYoun, Lee, JaeHyun
• Primary Examiner(s): Tornow, Mark
• Assistant Examiner(s): BOYLE, ABBIGALE A
• Application Number:
  US13/107,075
• Publication Number:
  US 20120286418A1
• Time in Patent Office: 2,706 Days
• Field of Search: 257E23049, 257E23059, 257E23135, 257E23136, 257666-786, 438108, 438620, 438613
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/03013 for holding or confining the bonding area, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/0332 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/0343 in solid form
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/10135 : Alignment aids
• CPC Class Codes: H01L 2224/10165 : Alignment aids
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 : Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11464 : Electroless plating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
• CPC Class Codes: H01L 2224/81139 : Guiding structures on the body
• CPC Class Codes: H01L 2224/8114 : Guiding structures outside the body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 2924/3841 : Solder bridging

Abstract

A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a conductive layer over the semiconductor die;

forming an insulating layer over the conductive layer;

depositing a conductive material within openings of the insulating layer to form a plurality of conductive pillars over the conductive layer and a plurality of rigid dummy pillars over the semiconductor die electrically isolated from the conductive layer and conductive pillars, wherein a height of the rigid dummy pillars is greater than a height of the conductive pillars;

disposing a bump material over the conductive pillars;

providing a substrate;

disposing the semiconductor die over the substrate after forming the conductive pillars and rigid dummy pillars with the rigid dummy pillars maintaining a fixed standoff distance between the semiconductor die and substrate; and

reflowing the bump material, wherein surface tension retains the bump material within a footprint of the conductive pillars and the fixed standoff distance reduces pressure on the bump material.

2. The method of claim 1, further including removing a remaining portion of the insulating layer leaving the conductive pillars disposed over the conductive layer.

3. The method of claim 1, further including depositing a mold underfill material between the semiconductor die and substrate.

4. The method of claim 1, wherein the height of the rigid dummy pillars is greater than the height of the conductive pillars to maintain the fixed standoff distance between the semiconductor die and substrate.