Manufacture method of low temperature poly-silicon array substrate

• US 10,101,620 B2
• Filed: 05/20/2016
• Issued: 10/16/2018
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Deng, Si, Guo, Yuan
• Primary Examiner(s): Vu, Vu A
• Application Number:
  US15/111,822
• Publication Number:
  US 20180067351A1
• Time in Patent Office: 879 Days
• Field of Search: 438 30
• CPC Class Codes: G02F 1/133516 Methods for their manufacture, e.g. printing, electro-deposition or photolithography
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

Claims

1. A manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:

step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;

step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;

step 3, coating a photoresist layer on the polysilicon layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in the middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;

employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon section in the NMOS region and a second polysilicon section in the PMOS region;

employing a dry etching apparatus to implement ashing treatment to the first photoresist layer and the second photoresist layer to completely remove the thin layer regions at the two sides on the first photoresist layer, and meanwhile, to make the thicknesses of the thick layer of the first photoresist layer and the second photoresist layer thinner;

employing remained thick layer region on the first photoresist layer and the second photoresist layer to be a mask to implement N type heavy doping to the two sides of the first polysilicon section to obtain two N type heavy doping regions;

step 4, depositing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer, and depositing a second metal layer on the gate isolation layer, and patterning the second metal layer to obtain a first gate and a second gate correspondingly above the first polysilicon section and the second polysilicon section, respectively;

employing the first gate to be a mask to implement N type light doping to the first polysilicon section to obtain two N type light doping regions respectively at inner sides of the two N type heavy doping regions, and a first channel region is formed in a region between the two N type heavy doping regions on the first polysilicon section;

step 5, employing a mask to implement P type heavy doping to two sides of the second polysilicon section to obtain two P type heavy doping regions, and a second channel region is formed in a region between the two P type heavy doping regions on the second polysilicon section;

step 6, depositing an interlayer insulation layer on the first gate, the second gate and the gate isolation layer, and patterning the interlayer insulation layer and the gate isolation layer to obtain a first via above the N type heavy doping region and a second via above the P type heavy doping region, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer;

step 7, depositing a third metal layer on the interlayer insulation layer, and patterning the third metal layer to obtain a first source, a first drain, a second source and a second drain, and the first source and the first drain respectively contact with the N type heavy doping region through the first via, and the second source and the second rain respectively contact with the P type heavy doping region through the second via;

step 8, forming a flat layer on the first source, the first drain, the second source, the second drain and the interlayer insulation layer, and patterning the flat layer to obtain a third via above the first drain;

step 9, depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;

step 10, depositing a passivation protective layer on the common electrode and the flat layer, and the passivation protective layer covers the third via on the flat layer, and then patterning the passivation protective layer to obtain a fourth via at a bottom of the third via on the passivation protective layer;

step 11, depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, and the pixel electrode contacts with the first drain through the fourth via.

2. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1, wherein in the step 2, the low temperature crystallization process is Excimer Laser Annealing or Metal-Induced Lateral Crystallization.

3. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1, wherein in the step 2, a specific operation of channel doping is:

coating a photoresist layer on the polysilicon layer, and employing a mask to implement exposure, development to the photoresist layer, and after removing the photoresist layer in the NMOS region, implementing P type light doping to the polysilicon layer in the entire NMOS region.

4. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1, wherein in the step 6, rapid thermal annealing is employed to implement the dehydrogenation and activation treatments to the interlayer insulation layer.

5. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1, wherein the substrate is a glass substrate;

material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper;

the buffer layer, the gate isolation layer, the interlayer insulation layer and the passivation protective layer are Silicon Oxide layers, Silicon Nitride layers or composite layers superimposed with Silicon Oxide layers and Silicon Nitride layers;

the flat layer is organic photoresist material.

6. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1, wherein material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is metal oxide.

7. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 6, wherein the metal oxide is Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide or Indium Germanium Zinc Oxide.

8. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1, wherein the ion doped by the N type heavy doping and the N type light doping is phosphorus ion or arsenic ion.

9. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 3, wherein the ion doped by the P type heavy doping and the P type light doping is boron ion or gallium ion.

10. A manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:

step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;

step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;

step 3, coating a photoresist layer on the polysilicon layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in the middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;

employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon section in the NMOS region and a second polysilicon section in the PMOS region;

employing a dry etching apparatus to implement ashing treatment to the first photoresist layer and the second photoresist layer to completely remove the thin layer regions at the two sides on the first photoresist layer, and meanwhile, to make the thicknesses of the thick layer of the first photoresist layer and the second photoresist layer thinner;

employing remained thick layer region on the first photoresist layer and the second photoresist layer to be a mask to implement N type heavy doping to the two sides of the first polysilicon section to obtain two N type heavy doping regions;

the method further comprises steps of;

step 4, depositing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer, and depositing a second metal layer on the gate isolation layer, and patterning the second metal layer to obtain a first gate and a second gate correspondingly above the first polysilicon section and the second polysilicon section, respectively;

employing the first gate to be a mask to implement N type light doping to the first polysilicon section to obtain two N type light doping regions respectively at inner sides of the two N type heavy doping regions, and a first channel region is formed in a region between the two N type heavy doping regions on the first polysilicon section;

step 5, employing a mask to implement P type heavy doping to two sides of the second polysilicon section to obtain two P type heavy doping regions, and a second channel region is formed in a region between the two P type heavy doping regions on the second polysilicon section;

step 6, depositing an interlayer insulation layer on the first gate, the second gate and the gate isolation layer, and patterning the interlayer insulation layer and the gate isolation layer to obtain a first via above the N type heavy doping region and a second via above the P type heavy doping region, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer;

step 7, depositing a third metal layer on the interlayer insulation layer, and patterning the third metal layer to obtain a first source, a first drain, a second source and a second drain, and the first source and the first drain respectively contact with the N type heavy doping region through the first via, and the second source and the second rain respectively contact with the P type heavy doping region through the second via;

step 8, forming a flat layer on the first source, the first drain, the second source, the second drain and the interlayer insulation layer, and patterning the flat layer to obtain a third via above the first drain;

step 9, depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;

step 10, depositing a passivation protective layer on the common electrode and the flat layer, and the passivation protective layer covers the third via on the flat layer, and then patterning the passivation protective layer to obtain a fourth via at a bottom of the third via on the passivation protective layer;

step 11, depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, and the pixel electrode contacts with the first drain through the fourth via;

wherein in the step 2, the low temperature crystallization process is Excimer Laser Annealing or Metal-Induced Lateral Crystallization;

wherein in the step 2, a specific operation of channel doping is;

coating a photoresist layer on the polysilicon layer, and employing a mask to implement exposure, development to the photoresist layer, and after removing the photoresist layer in the NMOS region, implementing P type light doping to the polysilicon layer in the entire NMOS region.

11. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 10, wherein in the step 6, rapid thermal annealing is employed to implement the dehydrogenation and activation treatments to the interlayer insulation layer.

12. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 10, wherein the substrate is a glass substrate;

material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper;

the buffer layer, the gate isolation layer, the interlayer insulation layer and the passivation protective layer are Silicon Oxide layers, Silicon Nitride layers or composite layers superimposed with Silicon Oxide layers and Silicon Nitride layers;

the flat layer is organic photoresist material.

13. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 10, wherein material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is metal oxide.

14. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 13, wherein the metal oxide is Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide or Indium Germanium Zinc Oxide.

15. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 10, wherein the ion doped by the N type heavy doping and the N type light doping is phosphorus ion or arsenic ion.

16. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 10, wherein the ion doped by the P type heavy doping and the P type light doping is boron ion or gallium ion.