Manufacture method of low temperature poly-silicon array substrate

  • US 10,101,620 B2
  • Filed: 05/20/2016
  • Issued: 10/16/2018
  • Est. Priority Date: 01/28/2016
  • Status: Active Grant
First Claim
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1. A manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:

  • step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;

    step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;

    step 3, coating a photoresist layer on the polysilicon layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in the middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;

    employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon section in the NMOS region and a second polysilicon section in the PMOS region;

    employing a dry etching apparatus to implement ashing treatment to the first photoresist layer and the second photoresist layer to completely remove the thin layer regions at the two sides on the first photoresist layer, and meanwhile, to make the thicknesses of the thick layer of the first photoresist layer and the second photoresist layer thinner;

    employing remained thick layer region on the first photoresist layer and the second photoresist layer to be a mask to implement N type heavy doping to the two sides of the first polysilicon section to obtain two N type heavy doping regions;

    step 4, depositing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer, and depositing a second metal layer on the gate isolation layer, and patterning the second metal layer to obtain a first gate and a second gate correspondingly above the first polysilicon section and the second polysilicon section, respectively;

    employing the first gate to be a mask to implement N type light doping to the first polysilicon section to obtain two N type light doping regions respectively at inner sides of the two N type heavy doping regions, and a first channel region is formed in a region between the two N type heavy doping regions on the first polysilicon section;

    step 5, employing a mask to implement P type heavy doping to two sides of the second polysilicon section to obtain two P type heavy doping regions, and a second channel region is formed in a region between the two P type heavy doping regions on the second polysilicon section;

    step 6, depositing an interlayer insulation layer on the first gate, the second gate and the gate isolation layer, and patterning the interlayer insulation layer and the gate isolation layer to obtain a first via above the N type heavy doping region and a second via above the P type heavy doping region, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer;

    step 7, depositing a third metal layer on the interlayer insulation layer, and patterning the third metal layer to obtain a first source, a first drain, a second source and a second drain, and the first source and the first drain respectively contact with the N type heavy doping region through the first via, and the second source and the second rain respectively contact with the P type heavy doping region through the second via;

    step 8, forming a flat layer on the first source, the first drain, the second source, the second drain and the interlayer insulation layer, and patterning the flat layer to obtain a third via above the first drain;

    step 9, depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;

    step 10, depositing a passivation protective layer on the common electrode and the flat layer, and the passivation protective layer covers the third via on the flat layer, and then patterning the passivation protective layer to obtain a fourth via at a bottom of the third via on the passivation protective layer;

    step 11, depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, and the pixel electrode contacts with the first drain through the fourth via.

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