Interface adjustment processes for a data storage device

• US 10,101,763 B2
• Filed: 07/29/2015
• Issued: 10/16/2018
• Est. Priority Date: 07/29/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Tzafrir, Yonatan
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US14/812,794
• Publication Number:
  US 20170031845A1
• Time in Patent Office: 1,175 Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence

Abstract

A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

Claims

1. A method comprising:

in a data storage device that includes a controller and a memory die, wherein the controller includes a host interface and a memory interface, performing by the controller;

storing an opcode pattern from the host interface in a comparator;

storing a status bit for a first adjustment process by a control register;

storing a reference information by a phase calibrator to the memory interface;

monitoring, by a query circuit, the control register to determine that the value of the status bit indicates a host device is to perform the first adjustment process by a query circuit;

receiving a message from the host device via the host interface, the message indicating that the host device is to perform the first adjustment process associated with the host interface; and

performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process at the host device,

wherein the host device performs the first adjustment process to calibrate a phase of a first timing signal associated with the host interface and the controller performs the second adjustment process to calibrate a phase of a second timing signal associated with the memory interface, and

wherein the second adjustment process configures the controller to update a file table, after erasing data from a storage region.

2. The method of claim 1, wherein the message includes a command that complies with an embedded MultiMedia Card (eMMC) standard.

3. The method of claim 1, wherein the message includes a command that complies with a Serial Advanced Technology Attachment (SATA) standard.

4. The method of claim 1, wherein the message includes a command that complies with a Universal Serial Bus (USB) standard.

5. The method of claim 1, wherein the second adjustment process includes:

writing data to a memory of the memory die in response to the message indicating that the host device is to initiate the first adjustment process, and

reading the data from the memory in response to the message indicating that the host device is to initiate the first adjustment process.

6. The method of claim 5, further comprising:

prior to writing the data to the memory, encoding the data at an error correction code (ECC) engine of the data storage device; and

after reading the data from the memory, decoding the data at the ECC engine.

7. The method of claim 1, wherein the second adjustment process includes

sending data to a latch of the memory die, and

retrieving the data from the latch.

8. The method of claim 1, wherein the second adjustment process includes receiving data from the host device via the host interface during the first adjustment process.

9. The method of claim 8, wherein the second adjustment process includes:

writing the data to a memory of the memory die, and

reading the data from the memory.

10. The method of claim 1, wherein:

the host device performs the first adjustment process to calibrate communications with the data storage device via the host interface, and

the controller performs the second adjustment process to enable the first adjustment process to compensate for effects on the host interface that are due to operations at the memory interface.