Integrated voltage regulator with in-built process, temperature and aging compensation

• US 10,103,719 B2
• Filed: 09/16/2015
• Issued: 10/16/2018
• Est. Priority Date: 07/22/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Pant, Sanjay, Raja, Tezaswi, Charnas, Andy
• Primary Examiner(s): Connolly, Mark
• Application Number:
  US14/856,191
• Publication Number:
  US 20170075402A1
• Time in Patent Office: 1,126 Days
• Field of Search: 713300, 713320, 713600
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

Claims

1. A method for regulating voltage for a processor, said method comprising:

requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor;

comparing the target clock frequency to a first signal to generate an error signal;

using the error signal, generating a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform; and

generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

2. The method of claim 1, further comprising:

providing the output voltage as an input to a dynamic voltage controlled oscillator.

3. The method of claim 2, wherein the dynamic voltage controlled oscillator generates the first signal, wherein the first signal is a clock signal with a first frequency, wherein the first frequency is an operating frequency of the processor, and wherein the first frequency is directly related to the output regulator voltage.

4. The method of claim 1, further comprising:

compensating the error signal through a proportional-integral-derivative (PID) controller to generate the duty cycle control signal; and

generating the periodic waveform from the duty cycle control signal using digital pulse-width modulation and power FETs.

5. The method of claim 1, wherein the requesting a target frequency value comprises a software application running on the processor requesting the target frequency value.

6. The method of claim 1, further comprising:

providing the output regulator voltage as an input to a critical path monitoring circuit, wherein the target clock frequency is not tied to the output regulator voltage, and wherein further the first signal is a delay value from the critical path monitoring circuit.

7. The method of claim 6, wherein the comparing is performed by a phase detector.

8. The method of claim 7, further comprising:

adjusting the output regulator voltage wherein the critical path monitoring circuit maintains the target clock frequency across all temperature and aging variations.

9. An apparatus for regulating processor voltage, said apparatus comprising:

a comparator, having a first input operable to be set at a target frequency value, and wherein the target frequency value determines a target clock frequency for clocking a processor;

a dynamic voltage controlled oscillator (DVCO) operable to generate a clock signal with a first frequency, wherein the first frequency is an operating frequency of the processor and is a second input to the comparator, wherein the first frequency is a function of the output regulator voltage, wherein the DVCO is powered by the output regulator voltage, and wherein the first frequency is compared with the target clock frequency using the comparator to generate an error signal; and

a circuit operable to generate an output regulator voltage using the error signal, wherein the output regulator voltage is operable to supply power to the processor.

10. The apparatus of claim 9, wherein the circuit comprises:

a proportional-integral-derivative (PID) controller operable to compensate the error signal to generate a duty cycle control signal.

11. The apparatus of claim 10, wherein the circuit further comprises:

a digital pulse-width modulation block and a pair of power FETs operable to convert the duty cycle control signal into a periodic waveform.

12. The apparatus of claim 11, wherein the circuit further comprises:

a discrete inductor, wherein the periodic waveform is operable to periodically switch the discrete inductor in order to generate the output regulator voltage.

13. The apparatus of claim 9, wherein the target frequency value originates from a software application running on the processor.

14. The apparatus of claim 9, wherein the target frequency value is converted to the target clock frequency using a phase-locked loop (PLL) module.