Preparation method for thin film transistor, preparation method for array substrate, array substrate, and display apparatus

• US 10,120,256 B2
• Filed: 12/31/2015
• Issued: 11/06/2018
• Est. Priority Date: 08/14/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Ye, Lulu, Liu, Huafeng, Lv, Jingping, Yang, Lei, Yang, Meng, Zhang, Kai, Wang, Chao, Sun, Chaochao, Zhao, Shengwei
• Primary Examiner(s): Kalam, Abul
• Application Number:
  US15/521,471
• Publication Number:
  US 20170329163A1
• Time in Patent Office: 1,041 Days
• Field of Search: None
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.

Claims

1. A method for manufacturing a thin-film transistor (TFT), comprising:

forming a pattern of a semiconductor layer on a base substrate;

forming an interlayer dielectric layer on the pattern of the semiconductor layer;

forming a first photoresist pattern on the interlayer dielectric layer, the first photoresist pattern including first-thickness photoresist and second-thickness photoresist;

the first-thickness photoresist corresponding to an area, at which a channel region is to be formed, in the pattern of the semiconductor layer;

the second-thickness photoresist corresponding to areas, at which a source lightly doped region and a drain lightly doped region are to be formed, in the pattern of the semiconductor layer;

the first-thickness photoresist has a thickness greater than that of the second-thickness photoresist;

performing heavily doped ion implantation on the pattern of the semiconductor layer by taking the first photoresist pattern as a barrier mask, and forming patterns of a source heavily doped region and a drain heavily doped region;

performing ashing treatment on the first photoresist pattern, so as to remove the second-thickness photoresist and reduce the thickness of the first-thickness photoresist, and form a second photoresist pattern;

performing lightly doped ion implantation on the pattern of the semiconductor layer by taking the second photoresist pattern as a barrier mask, and forming patterns of the channel region, the source lightly doped region and the drain lightly doped region; and

removing the second photoresist pattern.

2. The method for manufacturing the TFT according to claim 1, wherein a source of the TFT is formed by the source lightly doped region and the source heavily doped region;

a drain of the TFT is formed by the drain lightly doped region and the drain heavily doped region; and

the source and the drain has an interval therebetween so as to define the channel region.

3. The method for manufacturing the TFT according to claim 1, wherein the second-thickness photoresist is located on both sides of the first-thickness photoresist.

4. The method for manufacturing the TFT according to claim 1, wherein forming the first photoresist pattern includes:

forming a photoresist film, performing exposure and development on the photoresist film via a multi-tone mask, and forming the first photoresist pattern, the first photoresist pattern including a photoresist-completely-retained region and photoresist-partially-retained regions;

the photoresist-completely-retained region corresponding to the area, at which the channel region is to be formed, in the pattern of the semiconductor layer; and

the photoresist-partially-retained regions corresponding to the areas, at which the source lightly doped region and the drain lightly doped region are to be formed, in the pattern of the semiconductor layer.

5. The method for manufacturing the TFT according to claim 1, wherein the multi-tone mask includes any one of a half-tone mask and a gray-tone mask.

6. The method for manufacturing the TFT according to claim 1, further comprising forming a pattern of a gate electrode, wherein the pattern of the gate electrode is formed before forming of the pattern of the semiconductor layer.

7. The method for manufacturing the TFT according to claim 1, further comprising forming a buffer layer, wherein the buffer layer is disposed between the pattern of the gate electrode and the pattern of the semiconductor layer.

8. The method for manufacturing the TFT according to claim 1, wherein the material of the semiconductor layer includes polycrystalline silicon (poly-Si).

9. The method for manufacturing the TFT according to claim 1, wherein n-type doping is performed in the heavily doped ion implantation process and the lightly doped ion implantation process.

10. The method for manufacturing the TFT according to claim 9, wherein doped ions are phosphorus ions.

11. A method for manufacturing an array substrate, comprising the method for manufacturing the TFT according to claim 1.

12. The method for manufacturing the array substrate according to claim 11, wherein a source of the TFT is formed by the source lightly doped region and the source heavily doped region;

a drain of the TFT is formed by the drain lightly doped region and the drain heavily doped region; and

the source and the drain has an interval therebetween so as to define the channel region.

13. The method for manufacturing the array substrate according to claim 11, wherein the second-thickness photoresist is located on both sides of the first-thickness photoresist.

14. The method for manufacturing the array substrate according to claim 11, wherein forming the first photoresist pattern includes:

forming a photoresist film, performing exposure and development on the photoresist film via a multi-tone mask, and forming the first photoresist pattern, the first photoresist pattern including a photoresist-completely-retained region and photoresist-partially-retained regions;

the photoresist-completely-retained region corresponding to the area, at which the channel region is to be formed, in the pattern of the semiconductor layer; and

the photoresist-partially-retained regions corresponding to the areas, at which the source lightly doped region and the drain lightly doped region are to be formed, in the pattern of the semiconductor layer.

15. The method for manufacturing the array substrate according to claim 11, wherein the multi-tone mask includes any one of a half-tone mask and a gray-tone mask.