Array substrate, touch display panel and display apparatus containing the same, and method for driving the touch display panel

• US 10,120,502 B2
• Filed: 12/28/2015
• Issued: 11/06/2018
• Est. Priority Date: 08/13/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing Opto-Electronics Technology Company, BOE Technology Group Co., Ltd.
• Inventors: Yang, Shengji, Dong, Xue, Xue, Hailin, Chen, Xiaochuan, Wang, Haisheng, Liu, Yingming, Xu, Rui, Zhao, Weijie, Wang, Lei, Ding, Xiaoliang, Li, Changfeng
• Primary Examiner(s): Sherman, Stephen G
• Application Number:
  US15/122,798
• Publication Number:
  US 20170185222A1
• Time in Patent Office: 1,044 Days
• Field of Search: 345174
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G06F 2203/04111 Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes

Abstract

The present disclosure provides an array substrate. The array substrate includes a bottom substrate; a plurality of gate lines and a plurality of data lines arranged on the bottom substrate for defining a plurality of subpixel regions; and a plurality of common electrode pads, each common electrode pad being located in a corresponding subpixel region, wherein one or more of the common electrode pads form a self-capacitance electrode.

Claims

1. An array substrate, comprising:

a bottom substrate;

a plurality of gate lines and a plurality of data lines arranged on the bottom substrate for defining a plurality of subpixel regions; and

a plurality of common electrode pads, each common electrode pad being located in a corresponding subpixel region,

wherein;

two or more neighboring ones of the common electrode pads that are in a same row form at least a portion of a self-capacitance electrode,

the two or more neighboring ones of the common electrode pads in the same row are connected by a common electrode signal line through via holes,

the common electrode signal line and the plurality of gate lines are formed in a same layer, and

one of the plurality of gate lines and the common electrode signal line are arranged in a gap between two adjacent rows of the common electrode pads.

2. The array substrate according to claim 1, wherein

the self-capacitance electrode further includes at least another one of the common electrode pads that is in a different row than the two or more neighboring ones of the common electrode pads in the same row, the at least another one of the common electrode pads in a different row is connected to the two or more neighboring ones of the common electrode pads by a connecting structure.

3. The array substrate according to claim 2, wherein the connecting structure is located at an intersection of a gate line and a data line on the bottom substrate.

4. The array substrate according to claim 3, wherein the connecting structure and the common electrode pads are in a same layer and made of a same material.

5. The array substrate according to claim 1, further including an insulating layer positioned between a layer containing a common electrode pad and a layer containing a corresponding gate line.

6. The array substrate according to claim 5, wherein:

one of the via holes is formed in the insulating layer and connects a common electrode pad and a corresponding common electrode signal line.

7. The array substrate according to claim 6, wherein the via holes have a same size;

and distances between the via holes and corresponding common electrode pads are same.

8. The array substrate according to claim 1, wherein the common electrode signal line and the plurality of gate lines are made of a same material.

9. The array substrate according to claim 1, further comprising:

a processing unit applying common electrode signals on the common electrode pads during a display period.

10. The array substrate according to claim 1, wherein a distance between centers of two adjacent self-capacitance electrodes is about 10 mm.

11. The array substrate according to claim 1, wherein:

a length of the self-capacitance electrode along a row direction is about (3.85±

0.15) mm; and

a length of the self-capacitance electrode along a column direction is about (3.85±

0.15) mm.

12. The array substrate according to claim 11, wherein:

a ratio of the length of the self-capacitance electrode along the row direction to the length of the self-capacitance electrode along the column direction is greater than 95% and less than 105%.

13. The array substrate according to claim 1, further including a top substrate, a plurality of thin-film transistors (TFTs) and a plurality of pixel electrodes placed in the subpixel regions between the top substrate and the bottom substrate, a gate of a TFT being connected to a gate line, a source of the TFT being connected to a data line, and a drain of the TFT being connected to a pixel electrode.

14. A touch display panel, including one or more of the array substrates according to claim 1.

15. The touch display panel according to claim 14, comprises a processing unit for detecting a touch motion by reading signals from the self-capacitance electrode.

16. A display apparatus, including one or more of the display panels according to claim 14.

17. A method for driving a touch display panel according to claim 14, comprising:

in a display period, a processing unit applying a common electrode signal on the common electrode pads; and

in a touch-sensing period, the processing unit applying a touch signal on the self-capacitance electrodes and determining a location of the touch motion based on the capacitance change on the self-capacitance electrodes, wherein the touch display panel displays a frame during the display period and the touch sensing-period.

18. The method according to claim 17, wherein the touch signal is a periodic pulse signal.