Structure and process to tuck fin tips self-aligned to gates

• US 10,121,852 B2
• Filed: 10/26/2017
• Issued: 11/06/2018
• Est. Priority Date: 05/22/2015
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., He, Hong, Kanakasabapathy, Sivananda K., Karve, Gauri, Lie, Fee Li, Liu, Derrick, Seo, Soon-Cheon, Sieg, Stuart A.
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US15/794,616
• Publication Number:
  US 20180061941A1
• Time in Patent Office: 376 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming a gate structure straddling a semiconductor fin;

forming a dielectric material over the semiconductor fin and on sidewall surfaces of the gate structure;

forming a patterned material stack over the dielectric material, the patterned material stack having an opening that exposes one side of the gate structure;

cutting the semiconductor fin utilizing the patterned material stack and a portion of the dielectric material within the opening as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall; and

forming outer gate spacers, wherein one of the outer gate spacers contains a lower sidewall portion that directly contacts the entirety of the exposed end wall of the semiconductor fin portion.

2. The method of claim 1, wherein a portion of the opening exposes a portion of the dielectric material over the semiconductor fin.

3. The method of claim 2, wherein the cutting the semiconductor fin includes etching the exposed portion of the dielectric material over the semiconductor fin to expose a topmost surface of the gate structure and to provide inner gate spacers.

4. The method of claim 3, wherein each of the inner gate spacers straddles over the surface of the semiconductor fin portion, and wherein one of the inner gate spacers located in the opening has an outer edge that is vertically aligned to the end wall of the semiconductor fin portion.

5. The method of claim 3 wherein the inner gate spacers comprise a same dielectric material as the outer gate spacers.

6. The method of claim 3, wherein the inner gate spacers comprise a different dielectric material than the outer gate spacers.

7. The method of claim 3, wherein the outer gate spacer that contains the lower sidewall portion that directly contacts the entirety of the exposed end wall of the semiconductor fin portion has a bottommost surface that directly contacts a topmost surface of a substrate.

8. The method of claim 7, wherein the substrate comprises an insulator layer of a semiconductor-on-insulator substrate.

9. The method of claim 1, wherein the cutting the semiconductor fin includes one or more anisotropic etching processes.

10. The method of claim 1, wherein the gate structure is a functional gate structure.

11. The method of claim 1, wherein the gate structure is a sacrificial gate structure, and wherein the sacrificial gate structure is replaced with a functional gate structure after forming the outer gate spacers.

12. The method of claim 1, wherein the patterned material stack comprises, from bottom to top, an optical planarization material and an antireflective coating.

13. The method of claim 1, further comprising removing the patterned material stack after the cutting and prior to the forming of the outer gate spacers.

14. The method of claim 1, wherein the forming the outer gate spacers comprises deposition of a dielectric material and performing a spacer etch.

15. A method of forming a semiconductor structure, the method comprising:

forming a gate structure straddling a semiconductor fin;

forming a dielectric material over the semiconductor fin and on sidewall surfaces of the gate structure;

forming a patterned material stack over the dielectric material, the patterned material stack having an opening that exposes one side of the gate structure;

cutting the semiconductor fin utilizing the patterned material stack and a portion of the dielectric material within the opening as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall, wherein during the cutting the dielectric material is etched to provide inner spacers, wherein one of the inner spacer in the opening has an outer edge that is vertically aligned to the end wall of the semiconductor fin portion; and

forming outer gate spacers, wherein one of the outer gate spacers contains a lower sidewall portion that directly contacts the entirety of the exposed end wall of the semiconductor fin portion.