Physical layout and structure of RGBZ pixel cell unit for RGBZ image sensor
First Claim
Patent Images
1. A pixel unit cell comprising:
- a non-visible light photodiode region and exactly three visible light photodiode regions, wherein the non-visible light photodiode region and the exactly three visible light photodiode regions collectively form a rectangle;
a non-visible light capacitance region that is (i) associated with the non-visible light photodiode region, (ii) not associated with any other photodiode region, and (iii) formed at a corner of the non-visible light photodiode region that is shared with exactly one of the three visible light photodiode regions;
a non-visible light transfer gate positioned between the non-visible light photodiode region and the non-visible light capacitance region;
a single visible light capacitance region associated with the exactly three visible light photodiode regions; and
for each of the exactly three visible light photodiode regions, a respective visible light transistor gate positioned between the visible light photodiode region and the single visible light capacitive region at a corner of the visible light photodiode region that is shared with all of both other visible light photodiode regions and the non-visible light photodiode region, wherein no electrode is positioned between the non-visible light photodiode region and the single visible light capacitive region.
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Abstract
An image sensor is described having a pixel cell unit. The pixel cell unit has first, second and third transfer gate transistor gates on a semiconductor surface respectively coupled between first, second and third visible light photodiode regions and a first capacitance region. The pixel cell unit has a fourth transfer gate transistor gate on the semiconductor surface coupled between a first infrared photodiode region and a second capacitance region.
46 Citations
12 Claims
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1. A pixel unit cell comprising:
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a non-visible light photodiode region and exactly three visible light photodiode regions, wherein the non-visible light photodiode region and the exactly three visible light photodiode regions collectively form a rectangle; a non-visible light capacitance region that is (i) associated with the non-visible light photodiode region, (ii) not associated with any other photodiode region, and (iii) formed at a corner of the non-visible light photodiode region that is shared with exactly one of the three visible light photodiode regions; a non-visible light transfer gate positioned between the non-visible light photodiode region and the non-visible light capacitance region; a single visible light capacitance region associated with the exactly three visible light photodiode regions; and for each of the exactly three visible light photodiode regions, a respective visible light transistor gate positioned between the visible light photodiode region and the single visible light capacitive region at a corner of the visible light photodiode region that is shared with all of both other visible light photodiode regions and the non-visible light photodiode region, wherein no electrode is positioned between the non-visible light photodiode region and the single visible light capacitive region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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forming a non-visible light photodiode region and exactly three visible light photodiode regions on a semiconductor surface, wherein the non-visible light photodiode region and the exactly three visible light photodiode regions collectively form a rectangle; forming a non-visible light capacitance region that is associated with the non-visible light photodiode region and is not associated with any other photodiode region, on the semiconductor surface at a corner of the non-visible light photodiode region that is shared with exactly one of the three visible light photodiode regions; forming a non-visible light transfer gate positioned between the non-visible light photodiode region and the non-visible light capacitance region on the semiconductor surface; forming a single visible light capacitance region associated with the multiple visible light photodiode regions on the semiconductor surface; and for each of the exactly three visible light photodiode regions, forming a respective visible light transistor gate positioned between the visible light photodiode region and the single visible light capacitive region on the semiconductor surface at a corner of the visible light photodiode region that is shared with all of both other visible light photodiode regions and the non-visible light photodiode region, wherein no electrode is positioned between the non-visible light photodiode region and the single visible light capacitive region. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification