Fluid pressure activated electrical contact devices and methods

  • US 10,128,601 B1
  • Filed: 02/13/2018
  • Issued: 11/13/2018
  • Est. Priority Date: 10/25/2014
  • Status: Active Grant
First Claim
Patent Images

1. An microelectronic structure having CTE (co-efficient of thermal expansion) compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween and a spring structure spanning the gap and connecting the adjacent tiles, the spring structure configured to permit movement of the adjacent tiles relative to one another to provide compensation for thermal expansion or contraction of the tiles;

  • a respective opening extending through each substrate tile from the upper surface to an opposing lower surface;

    an electrically conductive post extending through each opening from the upper surface to the lower surface; and

    a device layer attached above the upper surfaces of the common plane.

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