System and method for reducing false preamble detection in a communication receiver

• US 10,129,011 B2
• Filed: 05/25/2017
• Issued: 11/13/2018
• Est. Priority Date: 02/17/2016
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Khan, Muhammad Kalimuddin, Mulvaney, Kenneth J., Quinlan, Philip P. E., O'Mahony, Shane
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US15/605,082
• Publication Number:
  US 20170264422A1
• Time in Patent Office: 537 Days
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.

Claims

1. A packet detection circuit comprising:

packet preamble detection circuit to indicate detection of a packet preamble based upon a succession of detected edge signals, each separated from an adjacent edge signal by at least a prescribed time interval, matching a prescribed preamble pattern; and

clearing circuitry to produce a signal to indicate false preamble detection in response to failure to receive packet information following an indication of an arrival of a packet preamble.

2. The packet detection circuit of claim 1,

wherein the packet preamble detection circuit includes,

a counter circuit configured to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed count;

and

a pattern matching circuit, coupled to the counter circuit, configured to match a sequence of detected edge signals, separated from each other by at least the prescribed time interval, with the prescribed pattern.

3. The packet detection circuit of claim 2,

wherein the pattern matching circuit includes,

a register configured to hold a sequence of detected edge signals separated from each other by at least the prescribed time interval;

and

a comparator configured to compare the sequence of detected edge signals, separated from each other by at least a prescribed time interval, with the prescribed pattern.

4. The packet detection circuit of claim 2,

wherein the pattern matching circuit includes,

a clock circuit that produces clock signal pulses in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval.

5. The packet detection circuit of claim 2,

wherein the pattern matching circuit includes,

a clock circuit that produces clock signal pulses in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval;

and

phase matching circuitry configured to align the produced clock signal pulses with detected edge signals.

6. The packet detection circuit of claim 5,

wherein the phase matching circuitry includes,

phase matching circuitry including a phase locked loop filter (PLL) coupled to receive a phase signal and to produce a PLL signal;

and

a phase detector coupled to receive the edge detection signals, the clock signal pulses and the PLL signal and to produce the phase signal.

7. The packet detection circuit of claim 1,

wherein the clearing circuitry includes,

a logic processing circuit to provide the signal to indicate false preamble detection in response to failure to receive the packet information following the pattern matching circuit detecting a packet preamble.

8. The packet detection circuit of claim 1,

wherein the packet information includes a sync signal.

9. The packet detection circuit of claim 1,

wherein the clearing circuitry includes,

a logic processing circuit to power up in response to the pattern matching circuit indicating a match of a sequence of detected edge signals, separated from each other by at least the prescribed time interval, with the prescribed pattern;

wherein the logic processing circuit to provide signal to indicate false preamble detection in response to failure to receive the packet information following the pattern matching circuit detecting a packet preamble.

10. The packet detection circuit of claim 1, further comprising circuitry configured to:

set at least one of an automatic frequency control (AFC) or an automatic gain control (AGC) in a free running mode; and

lock at least one of the AFC or AGC in response to detection of the packet preamble.

11. A packet detection circuit comprising:

a counter circuit configured to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed count;

a pattern matching circuit, coupled to the counter circuit, configured to match a sequence of detected edge signals, separated from each other by at least a prescribed time interval, with the prescribed pattern; and

a logic processing circuit to indicate false preamble detection in response to failure to receive the packet information following the pattern matching circuit detecting a packet preamble.

12. A packet detection method comprising:

providing a signal to indicate detection of a packet preamble based upon a succession of detected edge signals, each separated from an adjacent edge signal by at least a prescribed time interval, matching a prescribed preamble pattern; and

producing a signal to indicate false preamble detection in response to failure to receive packet information following an indication of an arrival of a packet preamble.

13. The packet detection method of claim 12 further including:

cyclically counting clock counts between successive detected edge signals to determine whether they are separated from each other by at least a prescribed count.

14. The packet detection method of claim 12 further including:

cyclically counting clock counts between successive detected edge signals to determine whether they are separated from each other by at least a prescribed count; and

matching a sequence of detected edge signals, separated from each other by at least the prescribed time interval, with the prescribed pattern.

15. The packet detection method of claim 12 further including:

producing clock signal pulses in response to a provided indication indicating successive detected edge signals separated from each other by at least the prescribed time interval; and

phase matching to align the produced clock signal pulses with detected edge signals.

16. The packet detection method of claim 12,

wherein producing a signal to indicate false preamble detection includes powering up a logic processing circuit in response to an indication of a pattern match of a sequence of detected edge signals, separated from each other by at least the prescribed time interval, with the prescribed pattern.

17. The packet detection method of claim 12,

wherein producing a signal to indicate false preamble detection includes producing a clearing interrupt signal.

18. The packet detection method of claim 12,

wherein the packet information includes a sync signal.

19. The packet detection method of claim 12 further including:

cyclically counting clock counts between successive detected edge signals; and

comparing the count reached between two successive detected edge signals with a threshold value.

20. The packet detection method of claim 12 further including:

cyclically counting clock counts between successive detected edge signals;

comparing the count reached between two successive detected edge signals with a threshold value matching the prescribed time interval;

producing clock signal pulses in response to a provided indication indicating successive detected edge signals separated from each other by at least the prescribed time interval; and

phase matching to align the produced clock signal pulses with detected edge signals.

21. The packet detection method of claim 12 further including:

setting at least one of an automatic frequency control (AFC) or an automatic gain control (AGC) in a free running mode; and

locking at least one of the AFC or AGC in response to detection of the packet preamble.

22. A packet detection method comprising:

cyclically counting clock counts between successive detected edge signals;

comparing the count reached between two of the successive detected edge signals with a threshold value matching a prescribed count;

producing clock signal pulses in response to a provided indication indicating that the two of the successive detected edge signals a separated from each other by at least the prescribed count;

phase matching to align the produced clock signal pulses with one of the successive detected edge signals; and

producing a signal to indicate false preamble detection in response to failure to receive packet information following an indication of an arrival of a packet preamble.