Semiconductor image sensor module and method of manufacturing the same

• US 10,129,497 B2
• Filed: 11/01/2017
• Issued: 11/13/2018
• Est. Priority Date: 06/02/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Iwabuchi, Shin, Motoyoshi, Makoto
• Primary Examiner(s): Lee, John
• Application Number:
  US15/801,076
• Publication Number:
  US 20180054583A1
• Time in Patent Office: 377 Days
• Field of Search: 2502081, 348294, 348300, 348301, 348302, 348308, 438 66, 438 67, 438 73, 438 74, 438107, 438108, 438109, 257443, 257444, 257447, 257734, 257737, 257738, 257777, 257778, 257780, 257E31054, 257E21499, 257258, 257291
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 : MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 29/788 : with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1425 : Converter
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H04N 23/54 : Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Claims

1. An imaging device, comprising:

a first substrate including a plurality of pixels, a first pixel of the plurality of pixels including a photoelectric converter, a wiring layer, and a plurality of transistors electrically connected to the photoelectric converter and the wiring layer;

a second substrate bonded to the first substrate, the second substrate including a plurality of analog/digital converters and a plurality of penetration connectors electrically connected to the plurality of analog/digital converters, the plurality of penetration connectors including a first penetration connector;

a third substrate including a memory circuit; and

a plurality of bumps including a first bump configured to electrically connect the first penetration connector to the memory circuit,

wherein the first substrate, the second substrate, and the third substrate are stacked and electrically connected to one another.

2. The imaging device according to claim 1, wherein the first bump is disposed between the second substrate and the third substrate.

3. The imaging device according to claim 1, wherein the photoelectric converter is electrically connected to a first transistor of the plurality of transistors.

4. The imaging device according to claim 1, wherein the plurality of analog/digital converters includes a first analog/digital converter electrically connected to the first penetration connector.

5. The imaging device according to claim 1, further comprising a first pad electrically connected to the first penetration connector.

6. The imaging device according to claim 5, wherein the first pad is electrically connected to the first bump.

7. The imaging device according to claim 6, further comprising a second pad electrically connected to the memory circuit.

8. The imaging device according to claim 7, wherein the second pad is electrically connected to the first bump.

9. The imaging device according to claim 8, wherein the first pad is bonded to the first bump, and the second pad is bonded to the second bump.

10. The imaging device according to claim 9, wherein the first bump is disposed between the first substrate and the second pad.

11. The imaging device according to claim 10, wherein the first pad, the first bump, and the second pad are disposed between the second substrate and the third substrate.

12. The imaging device according to claim 1, wherein the first penetration is disposed so as to penetrate from a first surface of the second substrate to a second surface of the second substrate which is opposed to the first surface.

13. The imaging device according to claim 1, wherein the second substrate is bonded to a surface of the wiring layer.

14. The imaging device according to claim 1, wherein the second substrate further includes a reference signal generation circuit configured to output a reference signal to a comparator of at least one of the plurality of analog/digital converters.

15. The imaging device according to claim 1, wherein the first substrate further includes a pixel drive circuit configured to output a driving signal to the first pixel.

16. The imaging device according to claim 1, wherein the memory circuit is a DRAM circuit.

17. The imaging device according to claim 1, wherein the first, second, and third substrates are semiconductor substrates.

18. The imaging device according to claim 1, wherein the first substrate, the second substrate, the plurality of bumps, and the third substrate are disposed in this order from a light incident side of the imaging device.