Method of manufacturing a semiconductor device having an impurity concentration

• US 10,134,853 B2
• Filed: 08/08/2017
• Issued: 11/20/2018
• Est. Priority Date: 06/19/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulze, Hans-Joachim
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US15/671,190
• Publication Number:
  US 20170358649A1
• Time in Patent Office: 469 Days
• Field of Search: 257335, 257330, 257 77, 257 43, 257655, 438446, 438407, 430 5
• CPC Class Codes: H01L 21/263 with high-energy radiation H01L21/261 takes precedence
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C., and forming a first load terminal structure at the first side of the semiconductor body.

Claims

1. A method of manufacturing a vertical semiconductor device, the method comprising:

irradiating a semiconductor body with particles through a first side of the semiconductor body;

removing part of impurities from an irradiated part of the semiconductor body by out-diffusion during a separate thermal treatment in a temperature range between 450°

C. to 1200°

C. wherein a vertical distance between the first side and a second side of the irradiated part ranges between 10 μ

m and 200 μ

m and wherein an average concentration of impurities in the first side is less than 60% of an average concentration of impurities in the second side;

forming a first load terminal structure at the first side of the semiconductor body;

forming a second load terminal structure at the second side of the semiconductor body opposite to the first side.

2. The method of claim 1, wherein the vertical semiconductor device is one of an insulated gate field effect transistor and an insulated gate bipolar transistor, the method further comprising:

forming a control terminal structure at the first side by forming a gate dielectric structure and a gate electrode structure at the first side;

forming one of a source and an emitter at the first side by introducing dopants through the first side; and

forming one of a drain and a collector at a second side of the semiconductor body opposite to the first side by introducing dopants through the second side.

3. The method of claim 1, wherein the impurities include at least one of nitrogen and carbon.