Switching system and method

• US 10,135,438 B2
• Filed: 12/16/2016
• Issued: 11/20/2018
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Ferfics Limited
• Original Assignee: Ferfics Limited
• Inventors: Heaney, Eugene, O'Sullivan, John, Kenney, Stephen
• Primary Examiner(s): Skibinski, Thomas
• Application Number:
  US15/381,875
• Publication Number:
  US 20170201250A1
• Time in Patent Office: 704 Days
• Field of Search: 327379-382, 327384, 327436, 327437, 327427, 327551, 327534, 327564, 327306-311, 327313, 333101, 333103, 333104, 333126, 333262, 333133, 438473, 257E21317, 4555521, 455 78, 455 80, 455 82, 455 83
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03H 11/04 Frequency selective two-port networks
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

The invention relates to a Radio Frequency System and method. A Radio Frequency (RF) system comprising a RF switch comprising a plurality of transistor switching elements implemented on Silicon on Insulator (SOI) for switching at least one or more RF signals and said SOI comprises a bulk substrate region and a buried oxide region. At least one filter is adapted to isolate the RF signal from the substrate and/or other high frequency signals or control signals present in the RF system. There is also provided a coupling capacitor adapted to cooperate with the filter to improve linearity of the transistor switch elements.

Claims

1. A Radio Frequency (RF) device comprising:

a RF switch comprising a plurality of transistor switching elements implemented on Silicon on Insulator (SOI);

a voltage generator including a charge pump configured to provide an output voltage;

a level shifter configured to receive the output voltage from the charge pump and perform level shifting;

an oscillator configured to provide a clock signal to the charge pump;

a filter coupled between the level shifter and the RF switch;

wherein the filter is configured to block unwanted signals between the RF switch and the level shifter;

a digital control block configured to control the on-off state of the transistor elements;

wherein the filter is between the digital control block and a gate of each of the transistor switching elements; and

wherein each filter is configured to block unwanted high power RF voltage signals from the RF switch from reaching the digital control block and to reduce non-linearities in the RF switch.

2. The RF device of claim 1;

wherein the unwanted signals comprise one of RF signals, high frequency signals, and control signals.

3. The RF device of claim 1;

wherein each transistor switching element comprises a resistor coupled to a gate region of the transistor switching element.

4. The RF device of claim 3;

wherein the filter is coupled between the level shifter and a gate of each of the transistor switching elements.

5. The RF device of claim 3 wherein a coupling capacitor is adapted to cooperate with said at least one filter to improve linearity of the transistor switch elements.

6. The RF device as claimed in claim 5 wherein a width of a first transistor in the RF switch is reduced to fit the coupling capacitor into the same switch area as an RF switch without the coupling capacitor.

7. The RF device as claimed in claim 3 wherein the at least one filter is coupled to a gate bias line of at least one of said transistor switching elements.

8. The RF device as claimed in claim 3 wherein the at least one filter is coupled to a gate bias line and body bias line of at least one of said transistor switching elements.

9. The RF device as claimed in claim 3 wherein gate and body bias signals are connected to the at least one filter which is connected to a bias resistor and connected to the source or drain of the switch transistor through a capacitor.

10. The RF device as claimed in claim 3 wherein partial filtering occurs locally at least one of the transistor switching elements.

11. The RF device as claimed in claim 3 wherein at least one transistor comprises a connected drain-source resistor (RDS) to improve the linearity performance of the RF system.

12. The RF device of claim 11 comprising metal interconnects to connect a drain of a first RDS transistor to a source of a next RDS transistor, the RDS transistors arranged in a series.

13. The RF device of claim 11 comprising metal interconnects to connect a drain of a first RDS transistor to a source of a next transistor, the RDS transistors arranged in a series, wherein at least one RDS transistor comprises a metal contact layer between the source and the drain regions and wherein a trench layer is positioned underneath the metal contact layers and/or metal interconnects tracks in the RF system.

14. The RF device of claim 3 wherein the plurality of transistors are arranged in a stacked configuration.

15. The RF device of claim 3 wherein the voltage regulator is a negative voltage generator.

16. The RF device as claimed in claim 15 wherein the negative voltage generator and the at least one filter comprises means to isolate the level shifter and the negative voltage generator from high power high frequency signals present in the RF device.

17. The RF device as claimed in claim 1 comprising a trench implant layer adapted with means for capturing free carriers at an interface between a bulk substrate region and a buried oxide region.

18. The RF device as claimed in claim 17 wherein the trench layer substantially surrounds at least one of the transistor switching elements.

19. A method of manufacturing the RF device of claim 1, the method comprising the steps of:

arranging the plurality of transistor switching elements implemented on Silicon on Insulator (SOI); and

positioning the filter.

20. The method of claim 19 comprising the step of implanting a trench implant layer between a substrate and a buried oxide region for capturing free carriers at an interface between a bulk substrate region and a buried oxide region.

21. The method of claim 19 comprising the step of implanting a trench implant layer wherein the trench implant layer substantially surrounds at least one of the transistor switching elements.