GIP type liquid crystal display device

• US 10,140,938 B2
• Filed: 07/25/2014
• Issued: 11/27/2018
• Est. Priority Date: 12/31/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: He, Jian
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): Nadkarni, Sarvesh J
• Application Number:
  US14/429,503
• Publication Number:
  US 20160035299A1
• Time in Patent Office: 1,586 Days
• Field of Search: None
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2310/021 Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A GIP liquid type of crystal display device includes a clock generating unit that provides K scan clock signals to a first driving subunit and K scan clock signals to a second driving subunit respectively according to a scan sequence to make the first/second driving subunit provides driving signals to odd/even numbered rows of gate lines. In a first scan sequence, the time sequence of the scan clock signals to scan the (2N)th row of gate line lags behind that of the scan clock signals to scan the (2N−1)th row of gate line by ½K of a cycle, while in a second scan sequence, the time sequence of the scan clock signals to scan the (2N−1)th row of gate line lags behind that of the scan clock signals to scan the (2N)th row of gate line by ½K of a cycle, wherein N is a natural number, K=2m, and m is a natural number.

Claims

1. A Gate-In-Panel (GIP) type of liquid crystal display device, comprising a display unit, a clock generator and a gate driving unit, wherein the gate driving unit is connected with the display unit and the clock generator respectively;

the display unit comprises a plurality of pixel units for image display and a plurality of rows of gate lines, every two rows of the gate lines constitute a gate line group and have a row of pixel units disposed therebetween, an odd numbered row of the gate line is connected with pixel units in an adjacent row and odd numbered columns, and an even numbered row of the gate line is connected with pixel units in an adjacent row and even columns;

the gate driving unit comprises a first driver and a second driver, the first driver is used to provide driving signals to odd numbered rows of the gate lines and the second driver is used to provide driving signals to even numbered rows of the gate lines;

the clock generator is used to provide K scan clock signals to the first driver and K scan clock signals to the second driver respectively according to a scan sequence to make the first/second driver provide driving signals to odd/even numbered rows of the gate lines;

scan sequences of odd numbered frames and even numbered frames are different, the scan sequence comprises a first scan sequence and a second scan sequence corresponding to the odd/even numbered frames or the even/odd numbered frames;

in the first scan sequence, the phase of the scan clock signals to scan the (2N)th row of the gate line lags behind that of the scan clock signals to scan the (2N−

1)th row of the gate line by ½

K of a cycle;

in the second scan sequence, the phase of the scan clock signals to scan the (2N−

1)th row of the gate line lags behind that of the scan clock signals to scan the (2N)th row of the gate line by ½

K of a cycle, where N is a natural number, K=2m, and m is a natural number.

2. The display device of claim 1, wherein an (i)th one of the K scan clock signals provided to the first driver is configured to make the first driver drive the [(2i−

1)+2K*j]th row of the gate line;

an (i)th one of the K scan clock signals provided to the second driver is used to make the second driver drive the [2i+2K*j]th row of the gate line; and

wherein i is a natural number less than or equal to K and j is a positive integer larger than or equal to zero.

3. The display device of claim 2, further comprising:

a voltage generator configured for providing a gate on voltage Vgon and a gate off voltage Vgoff to the clock generator that provides the scan clock signals with amplitude values greater than or equal to that of the gate off voltage Vgoff and less than or equal to that of the gate on voltage Vgon, and providing the gate off voltage Vgoff to the first driver and the second driver to shut off the gates of the pixel units not driven.

4. The display device of claim 2, further comprising a time sequence controller, wherein the time sequence controller is configured to provide 2K control signals, a first triggering signal, a second triggering signal and a scan sequence control signal to the clock generator;

and

the time sequence controller is configured to further generate data control signals and image data according to image signals and input control signals controlling the image signals.

5. The display device of claim 4, wherein the clock generator is further configured to:

determine the first scan sequence or the second scan sequence as the scan sequence according to the scan sequence control signal; and

generate a first scan triggering signal for initiation of the scan done by the first driver, according to the scan sequence and the first triggering signal, and generate a second scan triggering signal for initiation of the scan done by the second driver, according to the determined scan sequence and the second triggering signal; and

wherein if the first scan sequence is determined as the scan sequence, the time sequence of the second scan triggering signal lags behind that of the first scan triggering signal by ½

K of a cycle;

if the second scan sequence is determined as the scan sequence, the time sequence of the first scan triggering signal lags behind that of the second scan triggering signal by ½

K of a cycle.

6. The display device of claim 5, wherein the clock generator is further configured to generate the 2K scan clock signals in one-to-one correspondence with the 2K control signals, according to the determined scan sequence, the first scan triggering signal, the second scan triggering signal and the 2K control signals;

and

wherein a phase of the 1st one of the scan clock signals provided to the first driver lags behind that of the first scan triggering signal by ½

K of a cycle, and a phase of the 1st one of the scan clock signals provided to the second driver lags behind that of the second scan triggering signal by ½

K of a cycle.

7. The display device of claim 4, further comprising a source driver, wherein the source driver is connected with the source driver and the display unit respectively;

and

the source driver is configured to provide, according to the data control signals and the image data provided by the source driver, image data voltages corresponding to the image data to the display unit.

8. The display device of claim 7, further comprising a gray scale voltage generator, wherein the gray scale voltage generator is connected with the source driver and used to provide a gamma reference voltage to it.

9. The display device of claim 1, further comprising:

a voltage generator configured for providing a gate on voltage Vgon and a gate off voltage Vgoff to the clock generator that provides the scan clock signals with amplitude values greater than or equal to that of the gate off voltage Vgoff and less than or equal to that of the gate on voltage Vgon, and providing the gate off voltage Vgoff to the first driver and the second driver to shut off the gates of the pixel units not driven.

10. The display device of claim 9, further comprising a time sequence controller, wherein the time schedule controller is configured to provide 2K control signals, a first triggering signal, a second triggering signal and a scan sequence control signal to the clock generator;

and

the time sequence controller is configured to further generate data control signals and image data according to image signals and input control signals controlling the image signals.

11. The display device of claim 10, wherein the clock generator is further configured to:

determine the first scan sequence or the second scan sequence as the scan sequence according to the scan sequence control signal; and

generate a first scan triggering signal for initiation of the scan done by the first driver, according to the scan sequence and the first triggering signal, and generate a second scan triggering signal for initiation of the scan done by the second driver, according to the determined scan sequence and the second triggering signal; and

wherein if the first scan sequence is determined as the scan sequence, the time sequence of the second scan triggering signal lags behind that of the first scan triggering signal by ½

K of a cycle;

if the second scan sequence is determined as the scan sequence, the time sequence of the first scan triggering signal lags behind that of the second scan triggering signal by ½

K of a cycle.

12. The display device of claim 11, wherein the clock generator is further configured to generate the 2K scan clock signals in one-to-one correspondence with the 2K control signals, according to the determined scan sequence, the first scan triggering signal, the second scan triggering signal and the 2K control signals;

and

wherein a phase of the 1st one of the scan clock signals provided to the first driver lags behind that of the first scan triggering signal by ½

K of a cycle, and a phase of the 1st one of the scan clock signals provided to the second driver lags behind that of the second scan triggering signal by ½

K of a cycle.

13. The display device of claim 10, further comprising a source driver, wherein the source driver is connected with the source driver and the display unit respectively;

and

the source driver is configured to provide, according to the data control signals and the image data provided by the source driver, image data voltages corresponding to the image data to the display unit.

14. The display device of claim 13, further comprising a gray scale voltage generator, wherein the gray scale voltage generator is connected with the source driver and used to provide a gamma reference voltage to it.

15. The display device of claim 1, further comprising a time sequence controller, wherein the time sequence controller is configured to provide 2K control signals, a first triggering signal, a second triggering signal and a scan sequence control signal to the clock generator;

and

the time sequence controller is configured to further generate data control signals and image data according to image signals and input control signals controlling the image signals.

16. The display device of claim 15, wherein the clock generator is further configured to:

determine the first scan sequence or the second scan sequence as the scan sequence according to the scan sequence control signal; and

generate a first scan triggering signal for initiation of the scan done by the first driver, according to the scan sequence and the first triggering signal, and generate a second scan triggering signal for initiation of the scan done by the second driver, according to the determined scan sequence and the second triggering signal; and

wherein if the first scan sequence is determined as the scan sequence, the time sequence of the second scan triggering signal lags behind that of the first scan triggering signal by ½

K of a cycle;

if the second scan sequence is determined as the scan sequence, the time sequence of the first scan triggering signal lags behind that of the second scan triggering signal by ½

K of a cycle.

17. The display device of claim 16, wherein the clock generator is further configured to generate the 2K scan clock signals in one-to-one correspondence with the 2K control signals, according to the determined scan sequence, the first scan triggering signal, the second scan triggering signal and the 2K control signals;

and

wherein a phase of the 1st one of the scan clock signals provided to the first driver lags behind that of the first scan triggering signal by ½

K of a cycle, and a phase of the 1st one of the scan clock signals provided to the second driver lags behind that of the second scan triggering signal by ½

K of a cycle.

18. The display device of claim 15, further comprising a source driver, wherein the source driver is connected with the source driver and the display unit respectively;

and

the source driver is configured to provide, according to the data control signals and the image data provided by the source driver, image data voltages corresponding to the image data to the display unit.

19. The display device of claim 18, further comprising a gray scale voltage generator, wherein the gray scale voltage generator is connected with the source driver and used to provide a gamma reference voltage to it.