GIP type liquid crystal display device

  • US 10,140,938 B2
  • Filed: 07/25/2014
  • Issued: 11/27/2018
  • Est. Priority Date: 12/31/2013
  • Status: Active Grant
First Claim
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1. A Gate-In-Panel (GIP) type of liquid crystal display device, comprising a display unit, a clock generator and a gate driving unit, wherein the gate driving unit is connected with the display unit and the clock generator respectively;

  • the display unit comprises a plurality of pixel units for image display and a plurality of rows of gate lines, every two rows of the gate lines constitute a gate line group and have a row of pixel units disposed therebetween, an odd numbered row of the gate line is connected with pixel units in an adjacent row and odd numbered columns, and an even numbered row of the gate line is connected with pixel units in an adjacent row and even columns;

    the gate driving unit comprises a first driver and a second driver, the first driver is used to provide driving signals to odd numbered rows of the gate lines and the second driver is used to provide driving signals to even numbered rows of the gate lines;

    the clock generator is used to provide K scan clock signals to the first driver and K scan clock signals to the second driver respectively according to a scan sequence to make the first/second driver provide driving signals to odd/even numbered rows of the gate lines;

    scan sequences of odd numbered frames and even numbered frames are different, the scan sequence comprises a first scan sequence and a second scan sequence corresponding to the odd/even numbered frames or the even/odd numbered frames;

    in the first scan sequence, the phase of the scan clock signals to scan the (2N)th row of the gate line lags behind that of the scan clock signals to scan the (2N−

    1)th row of the gate line by ½

    K of a cycle;

    in the second scan sequence, the phase of the scan clock signals to scan the (2N−

    1)th row of the gate line lags behind that of the scan clock signals to scan the (2N)th row of the gate line by ½

    K of a cycle, where N is a natural number, K=2m, and m is a natural number.

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