Semiconductor device and method for manufacturing the same

• US 10,157,936 B2
• Filed: 09/05/2017
• Issued: 12/18/2018
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakakura, Masayuki
• Primary Examiner(s): Le, Thao P
• Application Number:
  US15/695,162
• Publication Number:
  US 20170365626A1
• Time in Patent Office: 469 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/42 Transparent materials

Abstract

It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.

Claims

1. A display device comprising:

a scan line and a signal line intersecting with each other;

a capacitor wiring having a light transmitting property;

an insulating layer;

a gate electrode layer, the gate electrode layer being in electrical contact with the scan line;

a semiconductor layer overlapping with the gate electrode layer and interposed between the gate electrode layer and the insulating layer;

a gate insulating layer interposed between the semiconductor layer and the gate electrode layer;

a source electrode layer and a drain electrode layer in electrical contact with the semiconductor layer;

a pixel electrode having transparency and being in electrical contact with the signal line through a serial connection comprising the source electrode layer, the semiconductor layer and the drain electrode layer; and

a capacitor overlapping with the pixel electrode at least partly, the capacitor comprising the capacitor wiring, a capacitor electrode, and a dielectric layer interposed between the capacitor wiring and the capacitor electrode.

2. The display device according to claim 1,

wherein the dielectric layer is formed from the gate insulating layer,

wherein the capacitor wiring is parallel to the scan line, and

wherein the capacitor electrode is island-shaped, substantially overlaps the capacitor wiring, is made from a same layer as the source electrode layer or the drain electrode layer, and is in electrical contact with the pixel electrode through a contact hole in the insulating layer.

3. The display device according to claim 1,

wherein the dielectric layer is formed from the insulating layer,

wherein the capacitor wiring, the source electrode layer, and the drain electrode layer are formed from a same layer, and

wherein the capacitor electrode is formed by the pixel electrode.

4. The display device according to claim 1, wherein the scan line and the signal line are transparent to visible light.

5. A display device comprising:

a scan line and a signal line intersecting with each other;

a capacitor wiring having a light transmitting property;

a gate electrode layer, the gate electrode layer being in electrical contact with the scan line;

a semiconductor layer over the gate electrode layer;

a gate insulating layer interposed between the gate electrode layer and the semiconductor layer;

a source electrode layer and a drain electrode layer in electrical contact with the semiconductor layer;

a pixel electrode having transparency and being in electrical contact with the signal line through a serial connection comprising the source electrode layer, the semiconductor layer and the drain electrode layer;

an insulating layer over the semiconductor layer; and

a capacitor overlapping with the pixel electrode at least partly, the capacitor comprising the capacitor wiring, a capacitor electrode, and the gate insulating layer interposed between the capacitor wiring and the capacitor electrode.

6. The display device according to claim 5,

wherein the capacitor electrode is formed from a same layer as the source electrode layer or the drain electrode layer, and

wherein the pixel electrode is in electrical contact with the capacitor electrode through the insulating layer.

7. The display device according to claim 5,

wherein the capacitor wiring is parallel to the scan line, and

wherein the capacitor electrode is island-shaped and mostly overlapping with the capacitor wiring.

8. The display device according to claim 5,

wherein the capacitor wiring is parallel to the scan line, and

wherein the capacitor electrode is island-shaped and mostly overlapping with the capacitor wiring, and is made from a same layer as the source electrode layer or the drain electrode layer.

9. The display device according to claim 5,

wherein the capacitor wiring is parallel to the scan line, and

wherein the capacitor electrode is island-shaped and mostly overlapping with the capacitor wiring, is made from a same layer as the source electrode layer or the drain electrode layer, and is in electrical contact with the pixel electrode.

10. The display device according to claim 5,

wherein the capacitor wiring is parallel to the scan line, and

wherein the capacitor electrode is island-shaped and mostly overlapping with the capacitor wiring, is made from a same layer as the source electrode layer or the drain electrode layer, and is in electrical contact with the pixel electrode through a contact hole in the insulating layer.

11. The display device according to claim 5, wherein the semiconductor layer comprises an oxide semiconductor.

12. A display panel comprising the display device according to claim 5, and further comprising:

a display portion formed over a substrate, the display portion comprising the semiconductor layer and the capacitor;

a counter-substrate and a sealant configured to seal the display portion between the substrate and the counter-substrate;

a driver circuit configured to drive the display portion; and

an FPC configured to connect the display portion to an exterior terminal.

13. The display device according to claim 5, wherein the scan line and the signal line are transparent to visible light.

14. A display device comprising:

a scan line and a signal line intersecting with each other;

a capacitor wiring having a light transmitting property;

a gate electrode layer, the gate electrode layer being in electrical contact with the scan line;

a semiconductor layer formed over the gate electrode layer;

a gate insulating layer interposed between the gate electrode layer and the semiconductor layer;

a source electrode layer and a drain electrode layer in electrical contact with the semiconductor layer;

a pixel electrode having transparency and being in electrical contact with the signal line through a serial connection comprising the source electrode layer, the semiconductor layer and the drain electrode layer;

an insulating layer over the semiconductor layer; and

a capacitor overlapping with the pixel electrode at least partly, the capacitor comprising the capacitor wiring, a capacitor electrode, and the insulating layer interposed between the capacitor wiring and the capacitor electrode.

15. The display device according to claim 14, wherein the source electrode layer and the drain electrode layer have transparency and comprise a layer formed from a same layer as the capacitor wiring.

16. The display device according to claim 14, wherein the capacitor wiring, the source electrode layer, and the drain electrode layer are formed from a same layer.

17. The display device according to claim 14, wherein the capacitor electrode is formed by the pixel electrode.

18. The display device according to claim 14,

wherein the capacitor wiring, the source electrode layer, and the drain electrode layer are formed from a same layer, and

wherein the capacitor electrode is formed by the pixel electrode.

19. The display device according to claim 14, wherein the semiconductor layer comprises an oxide semiconductor.

20. A display panel comprising the display device according to claim 14, further comprising:

a display portion formed over a substrate, the display portion comprising the semiconductor layer and the capacitor;

a counter-substrate and a sealant configured to seal the display portion between the substrate and the counter-substrate;

a driver circuit configured to drive the display portion; and

an FPC configured to connect the display portion to an exterior terminal.

21. The display device according to claim 14, wherein the scan line and the signal line are transparent to visible light.