Systems and methods for reducing high order hall plate sensitivity temperature coefficients

• US 10,162,017 B2
• Filed: 07/12/2016
• Issued: 12/25/2018
• Est. Priority Date: 07/12/2016
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Cesaretti, Juan Manuel
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Yodichkas, Khristopher
• Application Number:
  US15/207,903
• Publication Number:
  US 20180017637A1
• Time in Patent Office: 896 Days
• Field of Search: 324225, 324251
• CPC Class Codes: G01R 33/0029 Treating the measured signals, e.g. removing offset or noise
• CPC Class Codes: G01R 33/0082 Compensation, e.g. compensating for temperature changes
• CPC Class Codes: G01R 33/07 Hall effect devices

Abstract

The systems and methods described can reduce high order temperature coefficients on the Hall plate sensitivity. A temperature coefficient circuit may include a first amplifier to receive a first reference voltage generated in conjunction with a proportional to absolute temperature (PTAT) device and a second amplifier to receive a second reference voltage generated in conjunction with a complementary to absolute temperature (CTAT) device, the second amplifier having a second output node. A plurality of resistors may be disposed in a signal path between output node of the first amplifier and an output node of the second amplifier. The plurality of resistors may be coupled to at least one voltage-to-current converter through one or more resistors taps. The voltage-to-current converter may generate at least one current signal that can be operable to apply a multiplication factor or a division divisor to an amplifier coupled to the voltage-to-current converter.

Claims

1. A circuit comprising:

a semiconductor substrate;

an epitaxial layer disposed over a surface of the semiconductor substrate;

a Hall effect element, at least a portion of the Hall effect element disposed in the epitaxial layer disposed over the surface of the semiconductor substrate;

a current generator configured to generate a drive current that passes through the Hall effect element, wherein the current generator comprises;

a first resistor for receiving a reference voltage resulting in a reference current passing through the first resistor, the reference current related to the drive current, the first resistor disposed in the epitaxial layer, wherein a resistance of the first resistor, the reference current, and the drive current change in accordance with changes of a stress in the semiconductor substrate, wherein the first resistor comprises;

first and second pickups implanted upon and diffused into a first surface of the epitaxial layer; and

a first buried structure disposed under the first surface of the epitaxial layer and under the first and second pickups, wherein the first buried structure has a density of atoms that results in a first low resistance path with a first resistance lower than a resistance of the epitaxial layer, wherein the reference current passes from the first pickup, through a first region of the epitaxial layer, through the first buried structure, and through a second region of the epitaxial layer to the second pickup, wherein the circuit further comprises;

an amplifier coupled to the Hall effect element, the amplifier to receive a sensitivity signal from Hall effect element, the sensitivity signal having a first temperature coefficient, the amplifier to generate a compensated sensitivity signal, the compensated sensitivity signal having a second temperature coefficient; and

a temperature compensation circuit coupled to the amplifier, the temperature compensation circuit to generate a multiplication reference current and provide the multiplication reference current to the amplifier;

wherein the amplifier applies the multiplication reference current to the amplifier to generate the compensated sensitivity signal with the second temperature coefficient smaller than the first temperature coefficient of the sensitivity signal.

2. The circuit of claim 1, wherein the first resistor comprises a vertical epitaxial resistor.

3. The circuit of claim 1, wherein the first temperature coefficient comprises a 1^st order temperature coefficient, a 2^nd order temperature coefficient, or both.

4. The circuit of claim 1, wherein the amplifier comprises a front end amplifier comprised of a Gilbert cell, wherein the Gilbert cell is coupled to receive the multiplication reference current to apply a multiplication factor to the amplifier.

5. The circuit of claim 4, wherein the Hall effect element comprises a horizontal Hall effect element.

6. The circuit of claim 5, wherein the first resistor is coupled to a second amplifier to form a current source or a current sink.

7. The circuit of claim 6, further comprising a current mirror coupled to the second amplifier, wherein the current mirror comprises a reference leg though which the reference current passes, and a drive leg through which the drive current passes, wherein the drive current passing through the Hall effect element passes between a higher voltage terminal of the Hall effect element and a lower voltage terminal of the Hall effect element.

8. The circuit of claim 7, wherein the drive leg of the current mirror is coupled to the higher voltage terminal.

9. The circuit of claim 7, wherein the drive leg of the current mirror is coupled to the lower voltage terminal.

10. The circuit of claim 1, wherein the current generator further comprises:

a second resistor coupled in series or in parallel with the first resistor, the second resistor disposed in the epitaxial layer, wherein the second resistor comprises;

third and fourth pickups implanted upon and diffused into the first surface of the epitaxial layer; and

a second buried structure disposed under the first surface of the epitaxial layer and under the third and fourth pickups, wherein the second buried structure has the density of atoms that results in a second low resistance path with a second resistance lower than the resistance of the epitaxial layer, wherein at least a portion of the reference current passes from the third pickup, through a third region of the epitaxial layer, through the second buried structure, and through a fourth region of the epitaxial layer to the fourth pickup.

11. The electronic circuit of claim 10, wherein a first length dimension of the first buried structure is disposed parallel to a first edge of the Hall effect element and proximate to the Hall effect element, and wherein a second length dimension of the second buried structure is disposed parallel to a second edge of the Hall effect element and proximate to the Hall effect element, wherein the second length dimension of the second buried structure is arranged perpendicular to the first length dimension of the first buried structure.

12. A circuit comprising:

a semiconductor substrate;

an epitaxial layer disposed over a surface of the semiconductor substrate;

a Hall effect element, at least a portion of the Hall effect element disposed in the epitaxial layer disposed over the surface of the semiconductor substrate;

a current generator configured to generate a drive current that passes through the Hall effect element, wherein the current generator comprises;

a first resistor for receiving a reference voltage resulting in a reference current passing through the first resistor, the reference current related to the drive current, the first resistor disposed in the epitaxial layer, wherein a resistance of the first resistor, the reference current, and the drive current change in accordance with changes of a stress in the semiconductor substrate, wherein the first resistor comprises;

first and second pickups implanted upon and diffused into a first surface of the epitaxial layer; and

a first buried structure disposed under the first surface of the epitaxial layer and under the first and second pickups, wherein the first buried structure has a density of atoms that results in a first low resistance path with a first resistance lower than a resistance of the epitaxial layer, wherein the reference current passes from the first pickup, through a first region of the epitaxial layer, through the first buried structure, and through a second region of the epitaxial layer to the second pickup, wherein the circuit further comprises;

an amplifier coupled to the Hall effect element, the amplifier to receive a sensitivity signal from Hall effect element, the sensitivity signal having a first temperature coefficient, the amplifier to generate a compensated sensitivity signal, the compensated sensitivity signal having a second temperature coefficient; and

a temperature compensation circuit coupled to the amplifier, the temperature compensation circuit to generate a multiplication reference current and a division reference current and provide the multiplication reference current and the division reference current to the amplifier;

wherein the amplifier applies the multiplication reference current and the division reference current to the amplifier to generate the compensated sensitivity signal with the second temperature coefficient smaller than the first temperature coefficient of the sensitivity signal.

13. The circuit of claim 12, wherein the first resistor comprises a vertical epitaxial resistor.

14. The circuit of claim 12, wherein the first portion of the temperature coefficient comprises a 1^st order temperature coefficient of the Hall effect element and the second portion of the temperature coefficient is a 2^nd order temperature coefficient of the Hall effect element.

15. The circuit of claim 12, wherein the amplifier comprises a front end amplifier comprised of a Gilbert cell, wherein the Gilbert cell is coupled to receive the multiplication reference current to apply a multiplication factor to the amplifier.

16. The circuit of claim 15, wherein the Hall effect element comprises a horizontal Hall effect element.

17. The circuit of claim 16, wherein the first resistor is coupled to a second amplifier to form a current source or a current sink.

18. The circuit of claim 17, further comprising a current mirror coupled to the second amplifier, wherein the current mirror comprises a reference leg though which the reference current passes, and a drive leg through which the drive current passes, wherein the drive current passing through the Hall effect element passes between a higher voltage terminal of the Hall effect element and a lower voltage terminal of the Hall effect element.

19. The circuit of claim 18, wherein the drive leg of the current mirror is coupled to the higher voltage terminal.

20. The circuit of claim 18, wherein the drive leg of the current mirror is coupled to the lower voltage terminal.

21. The circuit of claim 12, wherein the current generator further comprises:

a second resistor coupled in series or in parallel with the first resistor, the second resistor disposed in the epitaxial layer, wherein the second resistor comprises;

third and fourth pickups implanted upon and diffused into the first surface of the epitaxial layer; and

a second buried structure disposed under the first surface of the epitaxial layer and under the third and fourth pickups, wherein the second buried structure has the density of atoms that results in a second low resistance path with a second resistance lower than the resistance of the epitaxial layer, wherein at least a portion of the reference current passes from the third pickup, through a third region of the epitaxial layer, through the second buried structure, and through a fourth region of the epitaxial layer to the fourth pickup.