Hardware apparatuses and methods for memory corruption detection

• US 10,162,694 B2
• Filed: 12/21/2015
• Issued: 12/25/2018
• Est. Priority Date: 12/21/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stark, Tomer, Gabor, Ron, Nuzman, Joseph, Sade, Raanan, Bigbee, Bryant E.
• Primary Examiner(s): Bonzo, Bryce P
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US14/977,354
• Publication Number:
  US 20170177429A1
• Time in Patent Office: 1,100 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 21/60 Protecting data
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

Claims

1. A hardware processor comprising:

an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory; and

a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

2. The hardware processor of claim 1, further comprising a control register to set the position to the first location or the second, different location.

3. The hardware processor of claim 1, further comprising a control register to set a memory corruption detection protected space for a subset of the memory.

4. The hardware processor of claim 3, wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to allow access to the block of the memory without a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is not within the memory corruption detection protected space for the subset of the memory.

5. The hardware processor of claim 3, wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to perform a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is within the memory corruption detection protected space for the subset of the memory.

6. The hardware processor of claim 1, further comprising a register to store a base address of a memory corruption detection table in the memory comprising the memory corruption detection value for the block.

7. The hardware processor of claim 1, wherein the position of the memory corruption detection value in the pointer is selectable between the first location, the second, different location, and a third, different location.

8. The hardware processor of claim 1, wherein the pointer comprises a linear address of the block of the memory.

9. A method comprising:

receiving a request to access a block of a memory through a pointer to the block of the memory; and

allowing access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

10. The method of claim 9, further comprising setting the position to the first location or the second, different location.

11. The method of claim 9, further comprising setting a memory corruption detection protected space for a subset of the memory.

12. The method of claim 11, wherein the pointer further comprises a memory corruption detection protected space value, and further comprising allowing access to the block of the memory without a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is not within the memory corruption detection protected space for the subset of the memory.

13. The method of claim 11, wherein the pointer further comprises a memory corruption detection protected space value, and further comprising perform a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is within the memory corruption detection protected space for the subset of the memory.

14. The method of claim 9, further comprising storing a base address of a memory corruption detection table in the memory comprising the memory corruption detection value for the block.

15. The method of claim 9, wherein the position of the memory corruption detection value in the pointer is selectable between the first location, the second, different location, and a third, different location.

16. The method of claim 9, wherein the pointer comprises a linear address of the block of the memory.

17. A system comprising:

a memory;

a hardware processor comprising an execution unit to execute an instruction to request access to a block of the memory through a pointer to the block of the memory; and

a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

18. The system of claim 17, further comprising a control register to set the position to the first location or the second, different location.

19. The system of claim 17, further comprising a control register to set a memory corruption detection protected space for a subset of the memory.

20. The system of claim 19, wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to allow access to the block of the memory without a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is not within the memory corruption detection protected space for the subset of the memory.

21. The system of claim 19, wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to perform a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is within the memory corruption detection protected space for the subset of the memory.

22. The system of claim 17, further comprising a register to store a base address of a memory corruption detection table in the memory comprising the memory corruption detection value for the block.

23. The system of claim 17, wherein the position of the memory corruption detection value in the pointer is selectable between the first location, the second, different location, and a third, different location.

24. The system of claim 17, wherein the pointer comprises a linear address of the block of the memory.