Devices and methods for dynamically tunable biasing to backplates and wells

• US 10,170,353 B2
• Filed: 06/27/2017
• Issued: 01/01/2019
• Est. Priority Date: 03/21/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zang, Hui, Chi, Min-hwa
• Primary Examiner(s): Kielin, Erik
• Application Number:
  US15/634,091
• Publication Number:
  US 20170294336A1
• Time in Patent Office: 553 Days
• Field of Search: None
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect

Abstract

Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

Claims

1. An intermediate semiconductor device comprising:

a wafer comprising

a silicon substrate,

at least one first oxide layer disposed on at least a portion of the wafer,

at least one silicon layer disposed on the at least one first oxide layer,

at least one second oxide layer disposed on the at least one silicon layer,

at least one recess in the wafer,

at least one third oxide layer disposed on the wafer, wherein the at least one recess in the wafer is filled with the at least one third oxide layer,

at least one opening in the at least one recess, the at least one opening having sidewalls and a bottom surface,

a high k dielectric layer disposed on the sidewalls and the bottom surface of the at least one opening,

a work function material (WFM) layer disposed on at least a portion of the high k dielectric layer, and

at least one cavity within the at least one opening, wherein the at least one cavity is filled with metal and the at least one opening is filled with oxide.

2. The device of claim 1, wherein the at least one recess comprises:

at least one deep trench isolation (DTI) recess; and

at least one shallow trench isolation (STI) recess.

3. The device of claim 1, wherein the at least one cavity is positioned between sidewalls of the WFM layer.

4. The device of claim 3, wherein the at least one third oxide layer has a width equal to a width of the WFM layer.

5. The device of claim 3, wherein the at least one third oxide layer has a width greater than a width of the WFM layer.

6. The device of claim 1, the device further comprising:

at least one cavity within the at least one opening, wherein the at least one cavity is filled with metal and the at least one opening is filled with oxide.

7. The device of claim 6, wherein the at least one cavity is positioned between sidewalls of a work function material (WFM) layer.

8. The device of claim 7, wherein the at least one third oxide layer has a width equal to a width of the WFM layer.

9. The device of claim 7, wherein the at least one third oxide layer has a width greater than a width of the WFM layer.

10. The device of claim 1, the device further comprising:

a high k dielectric layer disposed on the sidewalls and the bottom surface of the at least one opening;

a work function material (WFM) layer disposed on at least a portion of the high k dielectric layer; and

an organic planarization layer (OPL) disposed on the WFM layer and extending between sidewalls of the WFM layer, wherein the OPL fills a portion of the at least one opening.

11. The device of claim 10, wherein the OPL is recessed in the wafer below the first oxide layer.