Semiconductor device method of manufacture

• US 10,170,451 B2
• Filed: 12/11/2017
• Issued: 01/01/2019
• Est. Priority Date: 07/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Yu, Chen-Hua, Tsai, Po-Hao
• Primary Examiner(s): Moore, Whitney
• Application Number:
  US15/837,957
• Publication Number:
  US 20180102345A1
• Time in Patent Office: 386 Days
• Field of Search: None
• CPC Class Codes: H01L 21/3205 Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

encapsulating a semiconductor die, a first set of through vias, and a reference via with an encapsulant;

exposing the first set of through vias and the reference via with a planarization process on a first side of the semiconductor die;

connecting the first set of through vias on a second side of the semiconductor die opposite the first side to a second semiconductor die; and

after the connecting the first set of through vias, exposing a first surface of the reference via with a singulation process.

2. The method of claim 1, wherein the exposing the first surface of the reference via reduces a height of the reference via.

3. The method of claim 1, wherein the exposing the first surface of the reference via exposes a sidewall of the reference via.

4. The method of claim 1, further comprising forming a shield coating in electrical connection with the reference via.

5. The method of claim 4, wherein the forming the shield coating forms at least two layers of material.

6. The method of claim 4, wherein the forming the shield coating forms at least three layers of material.

7. A method of manufacturing a semiconductor device, the method comprising:

placing a semiconductor device adjacent to a first via and a second via;

encapsulating the semiconductor device, the first via, and the second via with an encapsulant;

planarizing the encapsulant, the first via, the second via, and the semiconductor device; and

reducing a first height of the second via without reducing a second height of the first via.

8. The method of claim 7, wherein the reducing the first height of the second via is performed at least in part a sawing process.

9. The method of claim 7, wherein the second height is between about 100 μ

m and about 300 μ

m.

10. The method of claim 9, wherein the first height is between about 80 μ

m and about 250 μ

m.

11. The method of claim 10, wherein the encapsulant has the second height.

12. The method of claim 7, further comprising depositing an adhesive layer in physical contact with the second via.

13. The method of claim 12, further comprising depositing a first metal layer in physical contact with the adhesive layer.

14. The method of claim 13, further comprising depositing a second metal layer in physical contact with the first metal layer, the first metal layer comprising a different material than the second metal layer.

15. A method of manufacturing a semiconductor device, the method comprising:

attaching a first semiconductor device to first vias located within a first integrated fan out package, the first integrated fan out package further comprising a first semiconductor die;

attaching a second semiconductor device to second vias located within a second integrated fan out package;

applying an underfill material between the first semiconductor device and the second semiconductor device; and

singulating the underfill material, wherein the singulating the underfill material exposes third vias within the first integrated fan out package.

16. The method of claim 15, wherein the singulating the underfill material exposes a sidewall of the third vias.

17. The method of claim 15, wherein the singulating the underfill material reduces a height of the third vias.

18. The method of claim 15, further comprising forming a shield coating over the third vias after the singulating the underfill material.

19. The method of claim 18, wherein the forming the shield coating comprises:

forming a layer of titanium; and

forming a layer of copper over the layer of titanium.

20. The method of claim 19, wherein the forming the shield coating further comprises forming a layer of nickel over the layer of copper.