Manufacturing method of semiconductor memory device

• US 10,170,630 B2
• Filed: 06/10/2015
• Issued: 01/01/2019
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Arai, Yasuyuki
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US14/735,687
• Publication Number:
  US 20150357473A1
• Time in Patent Office: 1,301 Days
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor
• CPC Class Codes: H10B 12/377 having a storage electrode extension located over the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.

Claims

1. A manufacturing method of a semiconductor device comprising:

forming a transistor comprises a gate electrode;

forming a cylindrical semiconductor consisting of an oxide semiconductor on and in contact with the gate electrode;

forming a gate insulating film covering a side surface and a top surface of the cylindrical semiconductor; and

forming a first conductor covering the side surface of the cylindrical semiconductor with the gate insulating film therebetween.

2. The manufacturing method according to claim 1, wherein the oxide semiconductor comprises indium, gallium and zinc.

3. The manufacturing method according to claim 1, wherein the first conductor is formed over a second conductor with the gate insulating film therebetween.

4. The manufacturing method according to claim 1, wherein a side surface of the first conductor is in contact with an insulator that is on and in contact with the gate insulating film.

5. The manufacturing method according to claim 1, further comprising:

removing a portion of the gate insulating film that covers the top surface of the cylindrical semiconductor, and

forming a second conductor on and in contact with the cylindrical semiconductor.

6. A manufacturing method of a semiconductor device comprising:

forming a transistor comprises a gate electrode;

forming a columnar semiconductor consisting of an oxide semiconductor on and in contact with the gate electrode;

forming a gate insulating film covering a side surface and a top surface of the columnar semiconductor; and

forming a first conductor covering the side surface of the columnar semiconductor with the gate insulating film therebetween.

7. The manufacturing method according to claim 6, wherein the oxide semiconductor comprises indium, gallium and zinc.

8. The manufacturing method according to claim 6, wherein the first conductor is formed over a second conductor with the gate insulating film therebetween.

9. The manufacturing method according to claim 6, wherein a side surface of the first conductor is in contact with an insulator that is on and in contact with the gate insulating film.

10. The manufacturing method according to claim 6, further comprising:

removing a portion of the gate insulating film that covers the top surface of the columnar semiconductor, and

forming a second conductor on and in contact with the columnar semiconductor.