Array substrate and display device

• US 10,176,774 B2
• Filed: 07/27/2016
• Issued: 01/08/2019
• Est. Priority Date: 10/30/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Byoungwoo, Yu, SangHee
• Primary Examiner(s): Lin, Chun-Nan
• Application Number:
  US15/220,911
• Publication Number:
  US 20170124972A1
• Time in Patent Office: 895 Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0434 Flat panel display in which a field is applied parallel to the display plane
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

Claims

1. An array substrate comprising:

a display area;

a non-display area outside of the display area;

a gate-in-panel (GIP) circuit in the non-display area;

a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit, the plurality of clock signal lines comprising a first clock signal line, a second clock signal line substantially surrounding the first clock signal line, a third clock signal line substantially surrounding the second clock signal line, a fourth clock signal line substantially surrounding the third clock signal line, a fifth clock signal line on at least one side of a respective one of the first to fourth clock signal lines, a sixth clock signal line on at least one side of a respective one of the first to fourth clock signal lines, a seventh clock signal line on at least one side of a respective one of the first to fourth clock signal lines, and an eighth clock signal line on at least one side of a respective one of the first to fourth clock signal lines; and

connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit,

wherein each of the plurality of clock signal lines is a ring shaped line,

wherein each of the first to fourth clock signal lines is connected to each of the fifth to eighth clock signal lines, respectively, via at least two contact holes.

2. The array substrate of claim 1, wherein each of the first to the fourth clock signal line has four sides.

3. The array substrate of claim 1, wherein the fifth to eighth clock signal lines are configured to work as external signal input lines.

4. The array substrate of claim 2, wherein each of the first to fourth clock signal lines comprises an auxiliary clock signal line connected to the ring shaped line.

5. The array substrate of claim 2, wherein the first to fourth clock signal lines are formed in the same layer or cross-sectional level and made of the same material as that of at least one among a gate electrode, source and drain electrodes, and a conductive layer disposed in a layer different from a layer in which the source and drain electrodes are disposed.

6. The array substrate of claim 1, wherein the fifth to eighth clock signal lines are formed in the same layer or cross-sectional level and made of the same material as that of one among a gate electrode, source and drain electrodes, and a conductive layer disposed in a layer different from a layer in which the source and drain electrodes are disposed.

7. The array substrate of claim 1, wherein the connection lines are configured to connect the plurality of clock signal lines to the GIP circuit via the at least two contact holes disposed on the plurality of clock signal lines.

8. A display device including a display area, and a bezel area surrounding the display area, the display device comprising:

a circuit structure in the bezel area to generate a gate signal and to supply the gate signal to a thin-film transistor of a pixel in the display area;

a first clock signal line in the bezel area to transfer a first clock signal to the circuit structure;

a second clock signal line surrounding the first clock signal in the bezel area, and configured to transfer a second clock signal to the circuit structure;

a first additional clock signal line on at least one side of the first clock signal line in the bezel area, connected to the first clock signal line;

a second additional clock signal line on at least one side of the second clock signal line in the bezel area, connected to the second clock signal line;

a first connection line between the circuit structure and the first clock signal line to connect the first clock signal line to the circuit structure;

a second connection line between the circuit structure and the second clock signal line to connect the second clock signal line to the circuit structure; and

wherein the first additional clock signal line and the second additional clock signal line are connected to the first and the second clock signal lines, respectively, via at least two contact holes.

9. The display device of claim 8, wherein the first and the second clock signal line are arranged in concentric square rings.

10. The display device of claim 8, wherein the first additional clock signal line and the second additional clock signal line are formed in a layer different from the first clock signal line and the second clock signal line.