Wireless power receiver with programmable power path

• US 10,177,602 B2
• Filed: 01/08/2015
• Issued: 01/08/2019
• Est. Priority Date: 01/08/2014
• Status: Active Grant

• Current Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Original Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Inventors: Akram, Hasnain, Yen, Yung-Chih, Riehl, Patrick Stanley, Satyamoorthy, Anand
• Primary Examiner(s): Gblende, Jeffrey
• Application Number:
  US15/037,051
• Publication Number:
  US 20160299521A1
• Time in Patent Office: 1,461 Days
• Field of Search: None
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H02J 7/00712 the cycle being controlled or terminated in response to electric parameters
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A synchronous rectifier using only n-channel devices in which the low-side switches are effectively cross-coupled using low-side comparators and the high-side switches perform an accurate zero-voltage-switching (ZVS) comparison. The charging path of each bootstrap domain is completed through the low-side switches, which are each always on for every half-cycle independent of loading. This scheme gives rectifier efficiency gain because a) each bootstrap domain receives maximum charging time, and b) the charging occurs through a switch rather than a diode. Both these factors ensure the bootstrap domain is fully charged, thereby reducing conduction losses through the rectifier switches. Furthermore, settings may be adjusted by software to optimize the resistive and capacitive losses of the rectifier. Using data for die temperature and operating frequency, software can create a feedback loop, dynamically adjusting rectifier settings in order to achieve the best possible efficiency.

Claims

1. A synchronous rectifier circuit comprising:

first and second high side switches coupled to first and second input nodes and an output node for outputting a rectified voltage;

first and second low side switches coupled to the first and second input nodes and a ground node;

first and second high side comparators that control the first and the second high side switches, respectively; and

first and second low side comparators that control the first and second low side switches, respectively, wherein the first low side switch is coupled to a first AC input of the second low side comparator and the second low side switch is coupled to a second AC input to the first low side comparator.

2. The synchronous rectifier circuit of claim 1, wherein the first and the second high side switches and the first and the second low side switches are N-Channel metal-oxide-semiconductor field effect transistors (MOSFETs).

8. The synchronous rectifier circuit of claim 1, wherein the first and second low side comparators have settings including threshold and hysteresis levels, and wherein the settings are dynamically adjustable.

9. The synchronous rectifier circuit of claim 8, wherein the settings are dynamically adjusted based on die temperature and operating frequency.

3. A synchronous rectifier circuit comprising:

first and second high side switches coupled to first and second input nodes and an output node for outputting a rectified voltage;

first and second low side switches coupled to the first and second input nodes and a ground node;

first and second high side comparators that control the first and the second high side switches, respectively;

first and second low side comparators that control the first and second low side switches, respectively, wherein the first low side switch is coupled to a first input of the second low side comparator and the second low side switch is coupled to a second input to the first low side comparator; and

first and second high side bootstrapping circuits that provide a bootstrap domain for the first and second high side comparators.

4. The synchronous rectifier circuit of claim 3, wherein a bootstrap-charging path for the first and second high side bootstrapping circuits is completed by the first and second low side switches.

5. The synchronous rectifier circuit of claim 4, wherein the first low side switch turns on during a first half cycle to charge the first high side bootstrapping circuit, and wherein the second low side switch turns on during a second half cycle to charge the second high side bootstrapping circuit.

6. The synchronous rectifier circuit of claim 4, wherein the first and second low side comparators turn on the first and second low side switches each cycle to complete the bootstrap-charging path independent from a loading of the synchronous rectifier circuit.

7. A synchronous rectifier circuit comprising:

first and second high side switches coupled to first and second input nodes and an output node for outputting a rectified voltage;

first and second low side switches coupled to the first and second input nodes and a ground node;

first and second high side comparators that control the first and the second high side switches, respectively; and

first and second low side comparators that control the first and second low side switches, respectively, wherein the first low side switch is coupled to a first input of the second low side comparator and the second low side switch is coupled to a second input to the first low side comparator,

wherein the first low side comparator controls the first low side switch by comparing a second input voltage on the second input node and a ground voltage plus an offset voltage, or wherein the second low side comparator controls the second low side switch by comparing a first input voltage on the first input node and a ground voltage plus an offset voltage.

10. A method comprising:

receiving an input power from first and second input nodes and outputting a rectified voltage onto an output node by a synchronous rectifier circuit, wherein the synchronous rectifier circuit comprises first and second high side switches coupled to the first and second input nodes and the output node, and wherein the synchronous rectifier circuit further comprises first and second low side switches coupled to the first and second input nodes and the ground node;

controlling the first and the second high side switches by first and second high side comparators, respectively; and

controlling the first and the second low side switches by first and second low side comparators, respectively, wherein the first low side switch is coupled to a first AC input of the second low side comparator and the second low side switch is coupled to a second AC input to the first low side comparator.

11. The method of claim 10, wherein the first and the second high side switches and the first and the second low side switches are N-Channel metal-oxide-semiconductor field effect transistors (MOSFETs).

17. The method of claim 10, further comprising:

dynamically adjusting settings of the first and second low side comparators including threshold and hysteresis levels.

18. The method of claim 17, wherein the settings are dynamically adjusted based on die temperature and operating frequency.

12. A method comprising:

receiving an input power from first and second input nodes and outputting a rectified voltage onto an output node by a synchronous rectifier circuit, wherein the synchronous rectifier circuit comprises first and second high side switches coupled to the first and second input nodes and the output node, and wherein the synchronous rectifier circuit further comprises first and second low side switches coupled to the first and second input nodes and the ground node;

controlling the first and the second high side switches by first and second high side comparators, respectively;

controlling the first and the second low side switches by first and second low side comparators, respectively, wherein the first low side switch is coupled to a first AC input of the second low side comparator and the second low side switch is coupled to a second AC input to the first low side comparator; and

providing a bootstrap domain for the first and second high side comparators by first and second high side bootstrapping circuits.

13. The method of claim 12, wherein a bootstrap-charging path for the first and second high side bootstrapping circuits is completed by the first and second low side switches.

14. The method of claim 13, wherein the first low side switch turns on during a first half cycle to charge the first high side bootstrapping circuit, and wherein the second low side switch turns on during a second half cycle to charge the second high side bootstrapping circuit.

15. The method of claim 13, wherein the first and second low side comparators turn on the first and second low side switches every cycle to complete the bootstrap-charging path independent from a loading of the synchronous rectifier circuit.

16. A method comprising:

receiving an input power from first and second input nodes and outputting a rectified voltage onto an output node by a synchronous rectifier circuit, wherein the synchronous rectifier circuit comprises first and second high side switches coupled to the first and second input nodes and the output node, and wherein the synchronous rectifier circuit further comprises first and second low side switches coupled to the first and second input nodes and the ground node;

controlling the first and the second high side switches by first and second high side comparators, respectively; and

controlling the first and the second low side switches by first and second low side comparators, respectively, wherein the first low side switch is coupled to a first AC input of the second low side comparator and the second low side switch is coupled to a second AC input to the first low side comparator,

wherein the first low side comparator controls the first low side switch by comparing a second input voltage on the second input node and a ground voltage plus an offset voltage or wherein the second low side comparator controls the second low side switch by comparing a first input voltage on the first input node and a ground voltage plus the offset voltage.