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Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid

DC CAFC
  • US 10,186,523 B2
  • Filed: 08/31/2018
  • Issued: 01/22/2019
  • Est. Priority Date: 03/09/2006
  • Status: Expired due to Fees
First Claim
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1. A semiconductor chip, comprising:

  • gate electrode features formed within a region of the semiconductor chip, the gate electrode features formed in part based on corresponding gate electrode feature layout shapes used as an input to a lithography process, the gate electrode feature layout shapes positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein all gate gridlines extend in a y-direction, wherein adjacent gate gridlines are separated from each other by a gate pitch, each gate electrode feature layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate electrode feature layout shape positioned thereon, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type;

    at least six gate contact structures formed within the region of the semiconductor chip, the at least six gate contact structures formed in part utilizing corresponding at least six gate contact structure layout shapes as an input to a lithography process, wherein at least six gate electrode features within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six gate contact structures, each of the at least six gate contact structure layout shapes having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in an x-direction, each of the at least six gate contact structure layout shapes positioned and sized to overlap both edges of the gate electrode feature layout shape corresponding to the gate electrode feature to which it is in physical and electrical contact; and

    a first-metal layer formed above top surfaces of the gate electrode features within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate electrode features, the first-metal layer separated from the top surfaces of the gate electrode features by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, wherein the first-metal structure layout shapes are positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, wherein all first-metal gridlines extend in the x-direction, wherein at least eight of the at least eight first-metal gridlines have at least one first-metal structure layout shape positioned thereon, each first-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner on an associated first-metal gridline,wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein electrical connections within the logic circuit collectively include at least five first-metal structures corresponding to at least five first-metal structure layout shapes respectively positioned on at least five different first-metal gridlines,wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein some diffusion regions within the region of the semiconductor chip are physically and electrically contacted by at least one diffusion contact structure, the at least one diffusion contact structure formed in part utilizing corresponding at least one diffusion contact structure layout shape as an input to a lithography process, each diffusion contact structure layout shape within the region positioned in a substantially centered manner along an associated diffusion contact gridline of a diffusion contact grid, the diffusion contact grid having a diffusion contact gridline-to-diffusion contact gridline spacing measured in the x-direction equal to the gate pitch.

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