Circuits and methods including dual gate field effect transistors

• US 10,187,011 B2
• Filed: 09/22/2017
• Issued: 01/22/2019
• Est. Priority Date: 03/19/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kumar, Vinod
• Primary Examiner(s): Muse, Ismail A
• Application Number:
  US15/713,145
• Publication Number:
  US 20180013389A1
• Time in Patent Office: 487 Days
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Claims

1. A method, comprising:

coupling source and drain terminals of a first dual gate field effect transistor to a first voltage;

coupling a primary gate of the first dual gate field effect transistor to a second voltage that is different than the first voltage; and

coupling a secondary gate of the first dual gate field effect transistor to a third voltage that is different than the first voltage and the second voltage,

wherein coupling the primary gate to the second voltage includes coupling the primary gate to an output of an operational amplifier.

2. The method of claim 1, further comprising:

coupling an output transistor to the output of the operational amplifier;

coupling a non-inverting input of the operational amplifier to a voltage divider; and

coupling a current source to the output transistor and an inverting input of the operational amplifier.

3. The method of claim 2 wherein coupling the source and drain terminals to the first voltage includes coupling the source and drain terminals to a power supply voltage, and coupling the secondary gate to the third voltage includes coupling the secondary gate to a ground voltage.

4. The method of claim 1 wherein the first dual gate field effect transistor is a PMOS transistor.

5. A method, comprising:

coupling source and drain terminals of a first dual gate field effect transistor to a first voltage;

coupling a primary gate of the first dual gate field effect transistor to a second voltage that is different than the first voltage;

coupling a secondary gate of the first dual gate field effect transistor to a third voltage that is different than the first voltage and the second voltage;

coupling source and drain terminals of a second dual gate field effect transistor to the first voltage;

coupling a primary gate of the second dual gate field effect transistor to the second voltage; and

coupling a secondary gate of the second dual gate field effect transistor to the third voltage,

wherein coupling the primary gates of the first and second dual gate field effect transistors to the second voltage includes coupling the primary gates to an output of a first stage of a charge pump phase locked loop circuit, the first stage operable to output the second voltage based on a received input signal at an input frequency.

6. The method of claim 5, further comprising:

forming a decoupling capacitor of the charge pump phase locked loop circuit by;

coupling source and drain terminals of a third dual gate field effect transistor to the third voltage; and

coupling a primary gate and a secondary gate of the third dual gate field effect transistor to the first voltage.

7. The method of claim 5 wherein the first and second dual gate field effect transistors are PMOS transistors.

8. The method of claim 5 wherein the secondary gate of at least one of the first and second dual gate field effect transistors is formed in an N-well.

9. The method of claim 5 wherein the secondary gate of at least one of the first and second dual gate field effect transistors is formed in a P-well.

10. A method, comprising:

forming a capacitive dual gate field effect transistor in an active layer of a silicon-on-insulator (SOI) substrate having a buried oxide layer overlying a doped region, the capacitive transistor including source and drain regions having substantially vertical profiles that are oriented perpendicular to the buried oxide layer, the transistor having a primary gate, and a secondary gate in the doped region;

forming a front side contact to the doped region of the transistor;

coupling the source and drain regions to a first voltage;

coupling the primary gate to an output of an operational amplifier, the operational amplifier configured to output a second voltage that is different than the first voltage; and

coupling the secondary gate to a third voltage that is different than the first voltage and the second voltage.

11. The method of claim 10 wherein the doped region is an N-well and the transistor is a p-type device.

12. The method of claim 10 wherein the doped region is a P-well and the transistor is an n-type device.

13. The method of claim 10, further comprising:

forming an interconnect that couples the source and drain regions to a power supply, the power supply configured to supply the first voltage; and

forming an interconnect that couples the doped region to ground.

14. The method of claim 10 wherein forming the capacitive dual gate field effect transistor further comprises:

forming, as a first capacitive dielectric, a primary gate oxide layer that is substantially thinner than the buried oxide layer; and

forming, adjacent to the primary gate oxide layer, the primary gate for applying a bias voltage across the first capacitive dielectric.

15. The method of claim 10, further comprising forming the SOI substrate, including:

doping a well in a silicon substrate; and

forming the buried oxide layer over the doped well as a second capacitive dielectric.

16. The method of claim 15 wherein doping the well forms the secondary gate fir applying a bias across the second capacitive dielectric.

17. A method, comprising:

coupling a supply voltage to source and drain terminals of a dual gate PMOS transistor formed on a doped substrate that includes a buried oxide layer;

applying a bias voltage to a primary gate of the dual gate PMOS transistor to control current in a channel region between the source and drain terminals;

grounding the doped substrate via a secondary gate; and

operating the dual gate PMOS transistor as an integrated capacitor,

wherein applying the bias voltage includes outputting the bias voltage from an output terminal of an operational amplifier.

18. The method of claim 17 wherein the dual gate transistor is a dual gate PMOS transistor.

19. The method of claim 17 wherein the supply voltage is within the range of about 1.2 and 3.3 V.