Silicon carbide semiconductor device and method for manufacturing same

• US 10,192,960 B2
• Filed: 06/10/2014
• Issued: 01/29/2019
• Est. Priority Date: 07/26/2013
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Wada, Keiji, Masuda, Takeyoshi, Tamaso, Hideto, Saitoh, Yu, Hiyoshi, Toru, Sakai, Mitsuhiko
• Primary Examiner(s): Kim, Jay C
• Application Number:
  US14/906,482
• Publication Number:
  US 20160181372A1
• Time in Patent Office: 1,694 Days
• Field of Search: 257 77
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Claims

1. A silicon carbide semiconductor device comprising:

a silicon carbide layer having a first main surface and a second main surface opposite to said first main surface; and

a metal region,

said silicon carbide layer including

a drift region that constitutes said first main surface and that has a first conductivity type,

a body region that is provided on said drift region and that has a second conductivity type different from said first conductivity type, and

a source region that is provided on said body region to be separated from said drift region, that constitutes said second main surface, and that has the first conductivity type,

said silicon carbide layer being provided with a trench including a first side wall portion and a first bottom surface, said first side wall portion extending from said second main surface to said drift region through said source region and said body region, said first bottom surface being in said drift region,

said silicon carbide layer including a second conductivity type region that is embedded in said drift region to face said first bottom surface and that has said second conductivity type,

said second conductivity type region being separated from said body region,

said second conductivity type region being electrically connected to said source region,

said metal region being in contact with said source region,

said source region and said second conductivity type region being electrically connected to each other via said metal region,

said silicon carbide layer being provided with a stepped portion including a second bottom surface and a second side wall portion, said second bottom surface being between said first main surface and said second main surface, said second side wall portion connecting said second bottom surface and said second main surface to each other,

said metal region being in contact with said source region in said second main surface and is in contact with said second bottom surface,

said second conductivity type region being arranged in a plane, and

said metal region being directly in contact with said second conductivity type region.

2. The silicon carbide semiconductor device according to claim 1, wherein

said silicon carbide layer includes a termination region and an element region surrounded by said termination region, and

said stepped portion is provided in said termination region.

3. The silicon carbide semiconductor device according to claim 2, wherein

said termination region has a guard ring region having said second conductivity type, and

said metal region is in contact with said guard ring region at said second bottom surface, and said guard ring region is in contact with said second conductivity type region.

4. The silicon carbide semiconductor device according to claim 3, wherein

said termination region includes a field stop region that surrounds said guard ring region when viewed in a plan view and that has said first conductivity type, and

said field stop region is spaced from said second main surface.

5. The silicon carbide semiconductor device according to claim 2, wherein said metal region is directly in contact with said second conductivity type region at said second bottom surface.

6. The silicon carbide semiconductor device according to claim 1, wherein

said silicon carbide layer includes a termination region and an element region surrounded by said termination region, and

said stepped portion is provided in said element region.

7. The silicon carbide semiconductor device according to claim 6, wherein said metal region is directly in contact with said second conductivity type region at said second bottom surface.

8. The silicon carbide semiconductor device according to claim 1, wherein said source region is in contact with said second conductivity type region via said body region and a JTE region having said second conductivity type.

9. The silicon carbide semiconductor device according to claim 1, wherein

said first bottom surface of said trench surrounds said drift region when viewed in a plan view.

10. A silicon carbide semiconductor device comprising:

a silicon carbide layer having a first main surface and a second main surface opposite to said first main surface; and

a metal region,

said silicon carbide layer including

a drift region that constitutes said first main surface and that has a first conductivity type,

a body region that is provided on said drift region and that has a second conductivity type different from said first conductivity type, and

a source region that is provided on said body region to be separated from said drift region, that constitutes said second main surface, and that has the first conductivity type,

said silicon carbide layer being provided with a trench including a first side wall portion and a first bottom surface, said first side wall portion extending from said second main surface to said drift region through said source region and said body region, said first bottom surface being in said drift region,

said silicon carbide layer including a second conductivity type region that is embedded in said drift region to face said first bottom surface and that has said second conductivity type,

said second conductivity type region being separated from said body region,

said second conductivity type region being electrically connected to said source region,

said second conductivity type region being arranged in a plane,

said metal region being directly in contact with said second conductivity type region,

said silicon carbide layer is provided with a stepped portion including a second bottom surface and a second side wall portion, said second bottom surface being between said first main surface and said second main surface, said second side wall portion connecting said second bottom surface and said second main surface to each other, and

said metal region is in contact with said source region in said second main surface and is in contact with said second bottom surface.

11. The silicon carbide semiconductor device according to claim 10, wherein said second conductivity type region has a mesh structure when viewed in a plan view.

12. The silicon carbide semiconductor device according to claim 11, wherein

said source region and said second conductivity type region are electrically connected to each other via said metal region.

13. The silicon carbide semiconductor device according to claim 11, wherein said source region is in contact with said second conductivity type region via said body region and a JTE region having said second conductivity type.

14. The silicon carbide semiconductor device according to claim 13, wherein

said first bottom surface of said trench extends to surround a polygonal cell when viewed in a plan view, and

when viewed in a plan view, said second conductivity type region is provided at a location at which an apex of said cell overlaps with said second conductivity type region.

15. The silicon carbide semiconductor device according to claim 11, wherein

said first bottom surface of said trench surrounds said drift region when viewed in a plan view.

16. The silicon carbide semiconductor device according to claim 10, wherein

said first bottom surface of said trench surrounds said drift region when viewed in a plan view.