System and method for ripple-free AC power determination

• US 10,197,605 B2
• Filed: 03/26/2015
• Issued: 02/05/2019
• Est. Priority Date: 03/26/2015
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Quiquempoix, Vincent, Brumann, Michael
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): Curtis, Sean
• Application Number:
  US14/669,232
• Publication Number:
  US 20160282391A1
• Time in Patent Office: 1,412 Days
• Field of Search: 324 7645, 324140 R-142, 363 40- 42, 307 66, 702 60- 61, 702 75, 341126, 341143, 341145, 708300
• CPC Class Codes: G01R 21/003 Measuring reactive component
• CPC Class Codes: G01R 21/06 by measuring current and voltage G01R21/08 - G01R21/133 take precedence
• CPC Class Codes: G01R 21/1331 Measuring real or reactive component, measuring apparent energy
• CPC Class Codes: G01R 23/165 using filters
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/36 simultaneously only, i.e. parallel type

Abstract

A power metering circuit includes a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency.

Claims

1. A power metering circuit, comprising:

a current input path for receiving an analog current input at a first analog to digital converter;

a voltage input path for receiving an analog voltage input at a second analog to digital converter;

a multiplier configured to multiply an output of the current input path and the voltage input path;

a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and

a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency, wherein the control circuit comprises a frequency detector and a programmable oscillator configured to receive an output of the frequency detector and to generate said sampling frequency, and wherein the frequency detector comprises a low pass filterfollowed by a zero-crossing detector and frequency counter.

2. A power metering circuit in accordance with claim 1, wherein a number of clock periods detected is a power of 2 multiple of the line frequency.

3. A power metering circuit in accordance with claim 1, the current input path and the voltage input path each including a highpass filter.

4. A power metering circuit in accordance with claim 3, wherein the voltage input path includes a selectable phase shifter.

5. A power metering circuit in accordance with claim 1, including an output pulse width modulator.

6. A power metering circuit, comprising:

a first input path for receiving one of an analog current input or an analog voltage input at a first analog to digital converter;

a second input path for receiving another of the analog voltage input or the analog current input at a second analog to digital converter;

a multiplier configured to multiply an output of the first input path and the second input path; and

a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency, and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a power of 2 multiple of the line frequency.

7. A power metering in accordance with claim 6, wherein the control circuit includes a phase locked loop configured to receive one of the analog current input and the analog voltage input and to generate said sampling frequency.

8. A power metering circuit in accordance with claim 6, wherein the control circuit comprises a frequency detector and a programmable oscillator configured to receive an output of the frequency detector and to generate said sampling frequency.

9. A power metering circuit in accordance with claim 6, the first input path and the second input path each including a high pass filter.

10. A power metering circuit in accordance with claim 9, wherein the first input path includes a selectable phase shifter.

11. A power metering circuit in accordance with claim 6, including an output pulse width modulator.

18. A power metering circuit in accordance with claim 6, further comprising a detector frequency detector comprising a low pass filter followed by a zero-crossing detector and frequency counter.

12. A method, comprising:

receiving an analog current input at a first analog to digital converter;

receiving an analog voltage input at a second analog to digital converter;

multiplying an output of the current input path and the voltage input path;

notch filtering an output of the multiplier with a stop band based on a line frequency; and

setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a power of 2 multiple of the line frequency.

13. A method in accordance with claim 12, wherein setting the sampling frequency includes using a phase locked loop configured to receive one of the analog current input and the analog voltage input.

14. A method in accordance with claim 13, wherein setting the sampling frequency comprises using a frequency detector and a programmable oscillator configured to receive an output of the frequency detector.

15. A method in accordance with claim 12, the current input path and the voltage input path each including a highpass filter.

16. A method in accordance with claim 15, wherein the voltage input path includes a selectable phase shifter.

17. A method in accordance with claim 12, further comprising detecting the line frequency with a detector frequency detector comprising a low pass filter followed by a zero-crossing detector and frequency counter.