Semiconductor device and electronic device

  • US 10,204,925 B2
  • Filed: 09/29/2015
  • Issued: 02/12/2019
  • Est. Priority Date: 10/06/2014
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a first circuit;

    a second circuit;

    a third circuit;

    a first wiring;

    a second wiring;

    a third wiring;

    a third transistor;

    a fourth transistor;

    a fifth transistor; and

    a second capacitor,wherein the first circuit is configured to store a first data,wherein the second circuit is configured to store a second data,wherein the third circuit is configured to store a third data,wherein each of the first circuit, the second circuit and the third circuit comprises a first transistor, a second transistor, and a first capacitor,wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor,wherein the first wiring is electrically connected to the other of the source and the drain of each of the first transistors of the first circuit and the second circuit,wherein the second wiring is electrically connected to a gate of the first transistors of the each of first circuit and third circuit,wherein the first transistor of each of the first circuit, the second circuit and the third circuit includes an oxide semiconductor in a channel formation region,wherein one of a source and a drain of the third transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring,wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of third transistor and a second capacitor,wherein the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring,wherein the third wiring is electrically connected to a back-gate of each of the first transistors of the first circuit, the second circuit and the third circuit, andwherein an erase signal is input to the third wiring.

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