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Wireless power transmitter having low noise and high efficiency, and related methods

  • US 10,211,720 B2
  • Filed: 11/08/2013
  • Issued: 02/19/2019
  • Est. Priority Date: 11/09/2012
  • Status: Active Grant
First Claim
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1. A wireless power transmitter, comprising:

  • a bridge inverter includinga first switch and a second switch coupled together with a first switching node therebetween, the first and second switches being in series between a first terminal and a second terminal, the first and second terminals to receive, at the first and second terminals, a DC power signal comprising a first terminal voltage and a second terminal voltage lower in magnitude than the first terminal voltage; and

    a first capacitor coupled between the first switching node and a first voltage;

    wherein the first switch is controlled by a first control signal, and the second switch is controlled by a second control signal;

    control logic configured to generate the first and second control signals to complementarily open and close the first switch and the second switch according to an operating frequency to generate an AC power signal from the DC power signal, the control logic generating the first and second control signals complimentarily opening and closing the first switch and the second switch with a first delay between generating the first control signal to open the first switch and generating the second control signal to close the second switch, and with a second delay between generating the second control signal to open the second switch and generating the first control signal to close the first switch; and

    a resonant tank operably coupled to the first switching node of the bridge inverter, the resonant tank configured to receive the AC power signal and generate an electromagnetic field responsive thereto;

    wherein each of the first and second delays is sufficient to prevent the first switch and the second switch being closed at the same time, a first switching node voltage increasing above the first terminal voltage during the second delay and decreasing below the second terminal voltage during the first delay;

    wherein a capacitance of the first capacitor is sufficient to lengthen, by a factor of at least 7.5, a length of time for the first switching node voltage to reach the first terminal voltage during the second delay.

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