Methods and apparatus for selectively extracting and loading register states

• US 10,216,254 B1
• Filed: 06/29/2016
• Issued: 02/26/2019
• Est. Priority Date: 06/29/2016
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rao, Shiva, Munday, David Alexander
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US15/197,448
• Time in Patent Office: 972 Days
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 11/203 using migration
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2048 where the redundant components share neither address space nor persistent storage
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2009/4557 Distribution of virtual machine instances; Migration and load balancing
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.

Claims

1. An integrated circuit on which an application is implemented, comprising:

a plurality of registers, wherein a subset of the plurality of registers comprises critical registers that store critical register states; and

an extracting and loading circuit configured to migrate the application to another integrated circuit by extracting the critical register states from the critical registers and transferring the extracted critical register states to the another integrated circuit, wherein the extracting and loading circuit is not coupled to other non-critical registers in the plurality of registers, and wherein the application is hosted on the another integrated circuit after the migration.

2. The integrated circuit of claim 1, wherein the extracting and loading circuit is configured to load data into the critical registers.

3. The integrated circuit of claim 1, wherein the extracting and loading circuit comprises:

multiplexing circuits inserted at inputs of the critical registers; and

de-multiplexing circuits inserted at outputs of the critical registers.

4. The integrated circuit of claim 1, further comprising:

combinational logic interposed between successive pairs of the critical registers, wherein the extracting and loading circuit comprises scan chain circuitry that selectively bypasses the combinational logic.

5. The integrated circuit of claim 1, further comprising:

configuration memory programmed to implement custom user functions, wherein the extracting and loading circuit comprises programming logic that configures the configuration memory during configuration operations and that extracts the critical register states from the critical registers during normal operation of the integrated circuit.

6. The integrated circuit of claim 1, wherein the extracting and loading circuit comprises a memory-mapped port coupled to the critical registers.

7. The integrated circuit of claim 1, wherein the extracting and loading circuit comprises a debug fabric.

8. The integrated circuit of claim 1, wherein the extracting and loading circuit comprises a finite state machine.

9. The integrated circuit of claim 1, wherein the extracting and loading circuit comprises control logic that extracts the critical register states onto an external memory that is coupled to the integrated circuit.

10. An integrated circuit, comprising:

a plurality of registers, wherein a subset of the plurality of registers comprises critical registers that store critical register states;

an extracting and loading circuit configured to extract the critical register states from the critical registers and to output the extracted critical register states to another integrated circuit external to the integrated circuit, wherein the extracting and loading circuit is not coupled to other non-critical registers in the plurality of registers; and

combinational logic interposed between successive pairs of the critical registers, wherein the extracting and loading circuit comprises scan chain circuitry that selectively bypasses the combinational logic.