High performance interconnect physical layer
First Claim
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1. An apparatus comprising:
- a receiver processor comprising an agent to support a layered protocol stack comprising physical layer logic, link layer logic, and protocol layer logic, wherein the agent is to;
receive a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;
intermittently enter a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;
receive a control code within the L0c interval; and
initiate a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.
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Abstract
A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
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Citations
19 Claims
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1. An apparatus comprising:
a receiver processor comprising an agent to support a layered protocol stack comprising physical layer logic, link layer logic, and protocol layer logic, wherein the agent is to; receive a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits; intermittently enter a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control; receive a control code within the L0c interval; and initiate a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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receiving a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits; intermittently entering a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control; receiving a control code within the L0c interval; and initiating a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes. - View Dependent Claims (16, 17)
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18. A system comprising:
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a first computing device; and a second computing device coupled to the first computing device by a link, wherein the second processor device comprises; link layer circuitry to receive a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits; state machine logic to intermittently enter a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control; physical layer circuitry to; identify a control code received from the first computing device within the L0c interval; and initiate a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes. - View Dependent Claims (19)
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Specification