Array substrate, display panel and display device

  • US 10,228,594 B2
  • Filed: 08/17/2015
  • Issued: 03/12/2019
  • Est. Priority Date: 04/24/2015
  • Status: Active Grant
First Claim
Patent Images

1. An array substrate, comprising:

  • gate regions;

    gate lines each connected to respective ones of the gate regions;

    data lines intersecting the gate lines;

    pixel electrodes defined by adjacent ones of the gate lines and adjacent ones of the data lines, each of the pixel electrodes being arranged next to a respective one of the gate regions; and

    common electrode lines having a same length direction as a length direction of the gate lines, each of the common electrode lines being arranged next to a respective one of the gate lines,wherein each of the gate lines traverses, in the length direction of the gate line, the respective gate regions connected to the gate line at a middle position of each of the respective gate regions in a length direction of the data lines,wherein each of the pixel electrodes has a retraction region retracted away from a corresponding one of the gate lines at an end of the pixel electrode closer to the corresponding gate line,wherein each of the common electrode lines has a plurality of recess sections for respective ones of the gate regions, each of the recess sections being recessed away from a respective one of the retraction regions such that the recess section is arranged opposite to the respective retraction region with respect to the respective gate region, each of the recess sections having a first portion extending in a direction away from the respective gate region, a second portion extending in the length direction of the common electrode line, and a third portion extending in a direction approaching the respective gate region, the first portion being connected, only at an end away from the respective gate region, to the third portion via the second portion, andwherein each of the pixel electrodes, at an end thereof opposite to the end where the retraction region is located, consists of;

    a protrusion region protruding away the end where the retraction region is located in the length direction of the data lines, the protrusion region not overlapping in the length direction of the data lines with the gate region next to the pixel electrode, anda non-protrusion region overlapping in the length direction of the data lines with the gate region next to the pixel electrode,wherein the protrusion region is farther from the end where the retraction region is located than a point of the non-protrusion region farthest from the end where the retraction region is located.

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