Array substrate, display panel and display device

• US 10,228,594 B2
• Filed: 08/17/2015
• Issued: 03/12/2019
• Est. Priority Date: 04/24/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Liu, Chong, Wang, Wei, Zhao, Haisheng, Peng, Zhilong, Xiao, Zhilian, Liu, Huanping
• Primary Examiner(s): Wright, Tucker J
• Application Number:
  US15/122,585
• Publication Number:
  US 20170068142A1
• Time in Patent Office: 1,303 Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel

Abstract

The present disclosure discloses an array substrate, a display panel and a display device. The array substrate includes gate regions, gate lines, data lines, pixel electrodes and common electrode lines. The common electrode lines and the gate lines have the same extension direction, the pixel electrodes are located in regions defined by adjacent gate lines and adjacent data lines, the gate lines traverse the gate regions in the extension direction that are located in the same row as the gate lines, and the pixel electrodes have a gap from the gate lines at ends thereof closer to the gate lines. As such, a portion of the gate region that extends to the pixel region has a reduced area and hence a reduced edge length. This way, during the cleaning of the active layer after formation, less active layer metal may remain at the edges of the gate region. Thereby, the array substrate fabrication process is improved, and a product yield rate of the array substrate is increased.

Claims

1. An array substrate, comprising:

gate regions;

gate lines each connected to respective ones of the gate regions;

data lines intersecting the gate lines;

pixel electrodes defined by adjacent ones of the gate lines and adjacent ones of the data lines, each of the pixel electrodes being arranged next to a respective one of the gate regions; and

common electrode lines having a same length direction as a length direction of the gate lines, each of the common electrode lines being arranged next to a respective one of the gate lines,

wherein each of the gate lines traverses, in the length direction of the gate line, the respective gate regions connected to the gate line at a middle position of each of the respective gate regions in a length direction of the data lines,

wherein each of the pixel electrodes has a retraction region retracted away from a corresponding one of the gate lines at an end of the pixel electrode closer to the corresponding gate line,

wherein each of the common electrode lines has a plurality of recess sections for respective ones of the gate regions, each of the recess sections being recessed away from a respective one of the retraction regions such that the recess section is arranged opposite to the respective retraction region with respect to the respective gate region, each of the recess sections having a first portion extending in a direction away from the respective gate region, a second portion extending in the length direction of the common electrode line, and a third portion extending in a direction approaching the respective gate region, the first portion being connected, only at an end away from the respective gate region, to the third portion via the second portion, and

wherein each of the pixel electrodes, at an end thereof opposite to the end where the retraction region is located, consists of;

a protrusion region protruding away the end where the retraction region is located in the length direction of the data lines, the protrusion region not overlapping in the length direction of the data lines with the gate region next to the pixel electrode, and

a non-protrusion region overlapping in the length direction of the data lines with the gate region next to the pixel electrode,

wherein the protrusion region is farther from the end where the retraction region is located than a point of the non-protrusion region farthest from the end where the retraction region is located.

2. The array substrate according to claim 1, wherein, in a layer where the gate regions are formed, each of the gate regions has a protrusion relative to the gate line to which the gate region is connected in a direction perpendicular to the length direction of the gate line.

3. The array substrate according to claim 1, further comprising common electrodes connected with the common electrode lines.

4. The array substrate according to claim 1, wherein the pixel electrodes are made of a transparent conductive metallic material.

5. A display panel, comprising the array substrate as claimed in claim 1.

6. A display device, comprising the display panel as claimed in claim 5.

7. An array substrate, comprising:

gate regions;

gate lines each connected to respective ones of the gate regions;

data lines intersecting the gate lines;

pixel electrodes defined by adjacent ones of the gate lines and adjacent ones of the data lines, each of the pixel electrodes being arranged next to a respective one of the gate regions; and

common electrode lines having a same length direction as a length direction of the gate lines, each of the common electrode lines being arranged next to a respective one of the gate lines,

wherein each of the gate lines traverses, in the length direction of the gate line, the respective gate regions connected to the gate line at a middle position of each of the respective gate regions in a length direction of the data lines,

wherein each of the pixel electrodes has a retraction region retracted away from a corresponding one of the gate lines at an end of the pixel electrode closer to the corresponding gate line, and

wherein each of the pixel electrodes, at an end thereof opposite to the end where the retraction region is located, consists of;

a protrusion region protruding away from the end where the retraction region is located in the length direction of the data lines, the protrusion region not overlapping in the length direction of the data lines with the gate region next to the pixel electrode, and

a non-protrusion region overlapping in the length direction of the data lines with the gate region next to the pixel electrode,

wherein the protrusion region is farther from the end where the retraction region is located than a point of the non-protrusion region farthest from the end where the retraction region is located.