Timing controller generating pseudo control data included in control packet and N-bit image data included in RGB packet

• US 10,229,626 B2
• Filed: 05/27/2016
• Issued: 03/12/2019
• Est. Priority Date: 05/29/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, ChangKun, Kim, JoungTae, Jung, TaeYoung
• Primary Examiner(s): Yang, Kwang-Su
• Application Number:
  US15/167,069
• Publication Number:
  US 20160351099A1
• Time in Patent Office: 1,019 Days
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/2037 with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/2044 using dithering

Abstract

A timing controller including a memory unit configured to store image data with respect to p*q sub-pixels defined using p numbers of data lines and q numbers of gate lines, a reception unit configured to receive, from a host, (n+m)-bit image data with respect to each of two or more of the sub-pixels, a controller configured to generate pseudo control data corresponding to m-bit image data of the two or more of the sub-pixels, and an output unit configured to output n-bit image data with respect to each of the sub-pixels to a digital unit of a data driving unit, and output the pseudo control data to an analog unit of the data driving unit.

Claims

1. A timing controller comprising:

a memory storing image data with respect to p*q sub-pixels defined using p numbers of data lines and q numbers of gate lines, wherein p is a positive integer of a multiple of three and q is a positive integer;

a receiver receiving, from a host, (n+m)-bit image data with respect to each of two or more of the sub-pixels, wherein n and m are positive integers;

a controller generating pseudo control data corresponding to m-bit image data of the two or more of the sub-pixels; and

an output unit outputting n-bit image data with respect to each of the sub-pixels to a digital unit of a data driving unit, and outputting the pseudo control data to an analog unit of the data driving unit,

wherein the pseudo control data is included in a control packet and the n-bit image data is included in an RGB data packet.

2. The timing controller of claim 1, wherein, when the m-bit image data of the two or more of the sub-pixels are the same, the controller is further configured to generate the m-bit image data as the pseudo control data.

3. The timing controller of claim 1, wherein, when the m-bit image data of the two or more of the sub-pixels are different, the controller is further configured to select one of a mode value, median value, and average value of the m-bit image data of the two or more of the sub-pixels so as to generate the selected value as the pseudo control data.

4. The timing controller of claim 1, wherein, when the m-bit image data of the two or more of the sub-pixels are different, the controller is further configured to generate m-bit image data of a first sub-pixel as the pseudo control data in an f-th frame, and generate m-bit image data of a second sub-pixel as the pseudo control data in an (f+1)-th frame, f being a positive integer.

5. The timing controller of claim 1, wherein the controller is further configured to generate m-bit image data of a first sub-pixel as the pseudo control data in a g-th gate line, and m-bit image data of a second sub-pixel as the pseudo control data in a (g+1)-th gate line, g being a positive integer.

6. The timing controller of claim 1, wherein the sub-pixels indicate each of red (R), green (G), and blue (B) colors and comprise a pixel, and

wherein the controller is further configured to set a representative value among the lower m bits and upper m bits of the R, G, and B sub-pixels as the pseudo control data.