Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate
First Claim
1. A semiconductor device, comprising:
- a semiconductor substrate;
an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;
a three-dimensional channel region disposed above the isolation pedestal;
one or more nanowires disposed in a vertical arrangement above the three-dimensional channel region;
a gate electrode stack at least partially surrounding the three-dimensional channel region, wherein the gate electrode stack further surrounds a channel region of each of the one or more nanowires;
source and drain regions disposed on either side of the three-dimensional channel region and above the isolation pedestal; and
a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the non-planar uppermost surface of the isolation pedestal.
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Abstract
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
28 Citations
3 Claims
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1. A semiconductor device, comprising:
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a semiconductor substrate; an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface; a three-dimensional channel region disposed above the isolation pedestal; one or more nanowires disposed in a vertical arrangement above the three-dimensional channel region; a gate electrode stack at least partially surrounding the three-dimensional channel region, wherein the gate electrode stack further surrounds a channel region of each of the one or more nanowires; source and drain regions disposed on either side of the three-dimensional channel region and above the isolation pedestal; and a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the non-planar uppermost surface of the isolation pedestal. - View Dependent Claims (2, 3)
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Specification