Gate driving circuits and liquid crystal devices

• US 10,235,958 B2
• Filed: 01/17/2017
• Issued: 03/19/2019
• Est. Priority Date: 12/30/2016
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Shi, Longqiang, Chen, Shu Jhih
• Primary Examiner(s): Lee, Jr., Kenneth B
• Application Number:
  US15/328,900
• Publication Number:
  US 20180211627A1
• Time in Patent Office: 791 Days
• Field of Search: None
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present disclosure relates to a gate driving circuit including N number of cascaded-connected GOA driving units, wherein the GOA driving units at each of the levels includes a pull-up control circuit, a pull-up circuit, a level transfer circuit, a boast capacitor, and a pull-down holding circuit. The pull-down holding circuit of the GOA driving unit of the n-th level and the pull-down holding circuit of the GOA driving unit of the (n+1)-th level are turned on alternatedly. The pull-down holding circuit of die GOA driving unit of the n-th level may keep the potential of the node within the GOA driving units at the n-th and the (n+1)-th level in the off state, wherein n=1, 3, 5, . . . , N−1, and N is an even number greater than one. The present disclosure also relates to a LCD including the above gate driving circuit.

Claims

1. A gate driving circuit, comprising:

N number of cascaded-connected GOA driving units, wherein the GOA driving units at each of the levels comprises a pull-up control circuit, a pull-up circuit, a level transfer circuit, a boast capacitor, and a pull-down holding circuit;

the pull-down holding circuit of the GOA driving unit of the n-th level and the pull-down holding circuit of the GOA driving unit of the (n+1)-th level are turned on alternatedly;

when the pull-down holding circuit of the GOA driving unit at the n-th level is turned on, the pull-down holding circuit of the GOA driving unit respectively connects output ends of the pull-up control circuit, the pull-up circuit, and the level transfer circuit of the GOA driving units at the n-th level and the GOA driving units at the (n+1)-th level to reference low-potential signals;

when the pull-down holding circuit of the GOA driving unit at the (n+1)-th level is turned on, the pull-down holding circuit respectively connects the output ends of the pull-up control circuit, the pull-up circuit, and the level transfer circuit of the GOA driving unit at the n-th level and the GOA driving unit at the (n+1)-th level to the reference low-potential signals;

wherein n=1, 3, 5, . . . , N−

1, and N is an even number greater than one;

wherein the pull-down holding circuit comprises a transistor control unit, a first switch module, and a second switch module, the first switch module, and the second switch module, respectively connect between the output ends of the pull-up control circuit, the pull-up circuit, the level transfer circuit, and the reference low-potential signals;

wherein the transistor control unit of the GOA driving unit of the n-th level provides first control signals to the first switch module of the GOA driving unit at the n-th level and the second switch module of the GOA driving unit at the (n+1)-th level, the transistor control unit of the GOA driving unit of the (n+1)-th level provides second control signals to the second switch module of the GOA driving unit at the n-th level and the first switch module of the GOA driving unit at the (n+1)-th level;

wherein the transistor control unit of the GOA driving unit at the n-th level and the transistor control unit of the GOA driving unit at the (n+1)-th level outputs the first control signals and the second control signals in an alternated manner.

2. The gate driving circuit as claimed in claim 1, wherein the transistor control unit of the GOA driving unit of the n-th level outputs the first control signals in accordance with the first pull-down clock signals, and the transistor control unit of the GOA driving unit of the (n+1)-th level outputs the second control signals in accordance with the second pull-down clock signals;

and

wherein the first pull-down clock signals and the second pull-down clock signals are logically inverted.

3. The gate driving circuit as claimed in claim 1, wherein the first switch module, comprises a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor, the second switch module, comprises a fourth pull-down transistor, a fifth pull-down transistor, and a sixth pull-down transistor;

wherein drains of the first pull-down transistor, the second pull-down transistor, the third pull-down transistor, the fourth pull-down transistor, the fifth pull-down transistor, and the sixth pull-down transistor respectively connects to the reference low-potential signals, sources of the first pull-down transistor and the fourth pull-down transistor respectively connect to the output end of the pull-up control circuit, the second pull-down transistor and the fifth pull-down transistor respectively connect to the output end of the level transfer circuit, sources of the third pull-down transistor and the sixth pull-down transistor respectively connect to the output end of the pull-up circuit;

with respect to the GOA driving units at the n-th level, gates of the first pull-down transistor, second pull-down transistor, and the third pull-down transistor connects to the first control signals, gates of the fourth pull-down transistor, the fifth pull-down transistor, and the sixth pull-down transistor connects to the second control signals; and

with respect to the GOA driving unit at the (n+1)-th level, gates of the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor connects to the second control signals, and gates of the fourth pull-down transistor, the fifth pull-down transistor, and the sixth pull-down transistor connects to the first control signals.

4. The gate driving circuit as claimed in claim 3, wherein the transistor control unit of the GOA driving unit of the n-th level outputs the first control signals in accordance with the first pull-down clock signals, and the transistor control unit of the GOA driving unit of the (n+1)-th level outputs the second control signals in accordance with the second pull-down clock signals;

and

wherein the first pull-down clock signals and the second pull-down clock signals are logically inverted.

5. The gate driving circuit as claimed in claim 4, wherein the transistor control unit, comprises a first controllable transistor, a second controllable transistor, a third controllable transistor, and a fourth controllable transistor, a gate and a source of the first controllable transistor are interconnected to receive the corresponding pull-down clock signals, a drain of the first controllable transistor connects to a source of the second controllable transistor, a drain of the second controllable transistor connects to the reference low-potential signals, a source of the third controllable transistor connects to the first controllable transistor to receive the pull-down clock signals, a drain of the third controllable transistor connects to a source of the fourth controllable transistor, a drain of the fourth controllable transistor connects to the reference low-potential signals;

with respect to the GOA driving unit of the n-th level, a drain of the first controllable transistor and a source of the third controllable transistor connects to the first pull-down clock signals, a gate of the second controllable transistor and a gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the n-th level, a drain of the third controllable transistor outputs the first control signals;

wherein with respect to the GOA driving unit of the (n+1)-th level, the sources of the first controllable transistor and the third controllable transistor connect to the second pull-down clock signals, the gate of the second controllable transistor and the gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, the drain of the third controllable transistor outputs the second control signals; and

the gate of the third controllable transistor of the GOA driving unit of the n-th level and the gate of the third controllable transistor of the GOA driving unit of the (n+1)-th level are interconnected.

6. The gate driving circuit as claimed in claim 2, wherein the transistor control unit, comprises a first controllable transistor, a second controllable transistor, a third controllable transistor, and a fourth controllable transistor, a gate and a source of the first controllable transistor are interconnected to receive the corresponding pull-down clock signals, a drain of the first controllable transistor connects to a source of the second controllable transistor, a drain of the second controllable transistor connects to the reference low-potential signals, a source of the third controllable transistor connects to the first controllable transistor to receive the pull-down clock signals, a drain of the third controllable transistor connects to a source of the fourth controllable transistor, a drain of the fourth controllable transistor connects to the reference low-potential signals;

with respect to the GOA driving unit of the n-th level, a drain of the first controllable transistor and a source of the third controllable transistor connects to the first pull-down clock signals, a gate of the second controllable transistor and a gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the n-th level, a drain of the third controllable transistor outputs the first control signals;

wherein with respect to the GOA driving unit of the (n+1)-th level, the sources of the first controllable transistor and the third controllable transistor connect to the second pull-down clock signals, the gate of the second controllable transistor and the gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, the drain of the third controllable transistor outputs the second control signals; and

the gate of the third controllable transistor of the GOA driving unit of the n-th level and the gate of the third controllable transistor of the GOA driving unit of the (n+1)-th level are interconnected.

7. The gate driving circuit as claimed in claim 5, wherein the transistor control unit, further comprises a fifth controllable transistor, a source of the fifth controllable transistor connects to the drain of the third controllable transistor, and a drain of the fifth controllable transistor connects to the reference low-potential signals;

and

a gate of the fifth controllable transistor of the GOA driving unit of the n-th level connects to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, and with respect to the GOA driving unit of the (n+1)-th level, the gate of the fifth controllable transistor connects to the output end of the pull-up control circuit of the GOA driving unit of the n-th level.

8. The gate driving circuit as claimed in claim 6, wherein the transistor control unit, further comprises a fifth controllable transistor, a source of the fifth controllable transistor connects to the drain of the third controllable transistor, and a drain of the fifth controllable transistor connects to the reference low-potential signals;

and

a gate of the fifth controllable transistor of the GOA driving unit of the n-th level connects to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, and with respect to the GOA driving unit of the (n+1)-th level, the gate of the fifth controllable transistor connects to the output end of the pull-up control circuit of the GOA driving unit of the n-th level.

9. The gate driving circuit as claimed in claim 2, wherein the transistor control unit, comprises a first controllable transistor, a second controllable transistor, a third controllable transistor, and a fourth controllable transistor, a gate and a source of the first controllable transistor are interconnected to receive the corresponding pull-down clock signals, a drain of the first controllable transistor connects to a source of the second controllable transistor, a drain of the second controllable transistor connects to the reference low-potential signals, a source of the third controllable transistor connects to the first controllable transistor to receive the pull-down clock signals, a drain of the third controllable transistor connects to a source of the fourth controllable transistor, a drain of the fourth controllable transistor connects to the reference low-potential signals;

the transistor control unit, further comprises a sixth controllable transistor, a source of the sixth controllable transistor connects to the drain of the first controllable transistor, a drain of the sixth controllable transistor connects to the reference low-potential signals;

with respect to the GOA driving unit of the n-th level, a drain of the first controllable transistor and a source of the third controllable transistor connects to the first pull-down clock signals, a gate of the second controllable transistor and a gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the n-th level, a drain of the third controllable transistor outputs the first control signals;

with respect to the GOA driving unit of the (n+1)-th level, the sources of the first controllable transistor and the third controllable transistor connect to the second pull-down clock signals, the gate of the second controllable transistor and the gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, the drain of the third controllable transistor outputs the second control signals.

10. The gate driving circuit as claimed in claim 4, wherein the transistor control unit, comprises a first controllable transistor, a second controllable transistor, a third controllable transistor, and a fourth controllable transistor, a gate and a source of the first controllable transistor are interconnected to receive the corresponding pull-down clock signals, a drain of the first controllable transistor connects to a source of the second controllable transistor, a drain of the second controllable transistor connects to the reference low-potential signals, a source of the third controllable transistor connects to the first controllable transistor to receive the pull-down clock signals, a drain of the third controllable transistor connects to a source of the fourth controllable transistor, a drain of the fourth controllable transistor connects to the reference low-potential signals;

the transistor control unit, further comprises a sixth controllable transistor, a source of the sixth controllable transistor connects to the drain of the first controllable transistor, a drain of the sixth controllable transistor connects to the reference low-potential signals;

with respect to the GOA driving unit of the n-th level, a drain of the first controllable transistor and a source of the third controllable transistor connects to the first pull-down clock signals, a gate of the second controllable transistor and a gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the n-th level, a drain of the third controllable transistor outputs the first control signals;

with respect to the GOA driving unit of the (n+1)-th level, the sources of the first controllable transistor and the third controllable transistor connect to the second pull-down clock signals, the gate of the second controllable transistor and the gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, the drain of the third controllable transistor outputs the second control signals.

11. The gate driving circuit as claimed in claim 9, wherein the transistor control unit, further comprises a fifth controllable transistor, a source of the fifth controllable transistor connects to the drain of the third controllable transistor, and a drain of the fifth controllable transistor connects to the reference low-potential signals;

and

a gate of the fifth controllable transistor of the GOA driving unit of the n-th level connects to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, and with respect to the GOA driving unit of the (n+1)-th level, the gate of the fifth controllable transistor connects to the output end of the pull-up control circuit of the GOA driving unit of the n-th level.

12. The gate driving circuit as claimed in claim 10, wherein the transistor control unit, further comprises a fifth controllable transistor, a source of the fifth controllable transistor connects to the drain of the third controllable transistor, and a drain of the fifth controllable transistor connects to the reference low-potential signals;

and

a gate of the fifth controllable transistor of the GOA driving unit of the n-th level connects to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, and with respect to the GOA driving unit of the (n+1)-th level, the gate of the fifth controllable transistor connects to the output end of the pull-up control circuit of the GOA driving unit of the n-th level.

13. The gate driving circuit as claimed in claim 1, wherein the pull-up control circuit comprises a first pull-up transistor and a second pull-up transistor, gates of the first pull-up transistor and the second pull-up transistor are interconnected to receive the first clock signals, a source of the first pull-up transistor receives the transfer signals of the (n−

4)-th level with respect to the n-th level, a drain of the first pull-up transistor connects to a source of the second pull-up transistor, a drain of the second pull-up transistor operates as an output end of the pull-up control circuit to output the gate control signals of the current level;

the pull-up circuit comprises a fourth pull-up transistor, a gate of the fourth pull-up transistor connects to the output end of the pull-up control circuit to receive the gate control signals, a source of the fourth pull-up transistor connects to the second clock signals, and a drain of the fourth pull-up transistor connects to the output end of the pull-up circuit to output the scanning driving signals of the current level;

the level transfer circuit comprises a transfer transistor, a gate of the transfer transistor connects to the output end of the pull-up control circuit to receive the gate control signals, a source of the transfer transistor connects to the second clock signals, a drain of the transfer transistor operates as the output end of the level transfer circuit to output the transfer signals of the current level;

the boast capacitor connects between the output end of the pull-up control circuit and the output end of the pull-up circuit; and

the second clock signals and the first clock signals are logically inverted.

14. A liquid crystal device (LCD), comprising:

a gate driving circuit comprising N number of cascaded-connected GOA driving units, wherein the GOA driving units at each of the levels comprises a pull-up control circuit, a pull-up circuit, a level transfer circuit, a boast capacitor, and a pull-down holding circuit;

the pull-down holding circuit of the GOA driving unit of the n-th level and the pull-down holding circuit of the GOA driving unit of the (n+1)-th level are turned on alternatedly;

when the pull-down holding circuit of the GOA driving unit at the n-th level is turned on, the pull-down holding circuit of the GOA driving unit respectively connects output ends of the pull-up control circuit, the pull-up circuit, and the level transfer circuit of the GOA driving units at the n-th level and the GOA driving units at the (n+1)-th level to reference low-potential signals;

when the pull-down holding circuit of the GOA driving unit at the (n+1)-th level is turned on, the pull-down holding circuit respectively connects the output ends of the pull-up control circuit, the pull-up circuit, and the level transfer circuit of the GOA driving unit at the n-th level and the GOA driving unit at the (n+1)-th level to the reference low-potential signals;

wherein n=1, 3, 5, . . . , N−

1, and N is an even number greater than one;

wherein the pull-down holding circuit comprises a transistor control unit, a first switch module, and a second switch module, the first switch module, and the second switch module, respectively connect between the output ends of the pull-up control circuit, the pull-up circuit, the level transfer circuit, and the reference low-potential signals;

wherein the transistor control unit of the GOA driving unit of the n-th level provides first control signals to the first switch module of the GOA driving unit at the n-th level and the second switch module of the GOA driving unit at the (n+1)-th level, the transistor control unit of the GOA driving unit of the (n+1)-th level provides second control signals to the second switch module of the GOA driving unit at the n-th level and the first switch module of the GOA driving unit at the (n+1)-th level;

wherein the transistor control unit of the GOA driving unit at the n-th level and the transistor control unit of the GOA driving unit at the (n+1)-th level outputs the first control signals and the second control signals in an alternated manner.

15. The LCD as claimed in claim 14, wherein the transistor control unit of the GOA driving unit of the n-th level outputs the first control signals in accordance with the first pull-down clock signals, and the transistor control unit of the GOA driving unit of the (n+1)-th level outputs the second control signals in accordance with the second pull-down clock signals;

and

wherein the first pull-down clock signals and the second pull-down clock signals are logically inverted.

16. The LCD as claimed in claim 14, wherein the first switch module, comprises a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor, the second switch module, comprises a fourth pull-down transistor, a fifth pull-down transistor, and a sixth pull-down transistor;

wherein drains of the first pull-down transistor, the second pull-down transistor, the third pull-down transistor, the fourth pull-down transistor, the fifth pull-down transistor, and the sixth pull-down transistor respectively connects to the reference low-potential signals, sources of the first pull-down transistor and the fourth pull-down transistor respectively connect to the output end of the pull-up control circuit, the second pull-down transistor and the fifth pull-down transistor respectively connect to the output end of the level transfer circuit, sources of the third pull-down transistor and the sixth pull-down transistor respectively connect to the output end of the pull-up circuit;

with respect to the GOA driving units at the n-th level, gates of the first pull-down transistor, second pull-down transistor, and the third pull-down transistor connects to the first control signals, gates of the fourth pull-down transistor, the fifth pull-down transistor, and the sixth pull-down transistor connects to the second control signals; and

with respect to the GOA driving unit at the (n+1)-th level, gates of the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor connects to the second control signals, and gates of the fourth pull-down transistor, the fifth pull-down transistor, and the sixth pull-down transistor connects to the first control signals.

17. The LCD as claimed in claim 16, wherein the transistor control unit of the GOA driving unit of the n-th level outputs the first control signals in accordance with the first pull-down clock signals, and the transistor control unit of the GOA driving unit of the (n+1)-th level outputs the second control signals in accordance with the second pull-down clock signals;

and

wherein the first pull-down clock signals and the second pull-down clock signals are logically inverted.

18. The LCD as claimed in claim 17, wherein the transistor control unit, comprises a first controllable transistor, a second controllable transistor, a third controllable transistor, and a fourth controllable transistor, a gate and a source of the first controllable transistor are interconnected to receive the corresponding pull-down clock signals, a drain of the first controllable transistor connects to a source of the second controllable transistor, a drain of the second controllable transistor connects to the reference low-potential signals, a source of the third controllable transistor connects to the first controllable transistor to receive the pull-down clock signals, a drain of the third controllable transistor connects to a source of the fourth controllable transistor, a drain of the fourth controllable transistor connects to the reference low-potential signals;

with respect to the GOA driving unit of the n-th level, a drain of the first controllable transistor and a source of the third controllable transistor connects to the first pull-down clock signals, a gate of the second controllable transistor and a gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the n-th level, a drain of the third controllable transistor outputs the first control signals;

wherein with respect to the GOA driving unit of the (n+1)-th level, the sources of the first controllable transistor and the third controllable transistor connect to the second pull-down clock signals, the gate of the second controllable transistor and the gate of the fourth controllable transistor respectively connect to the output end of the pull-up control circuit of the GOA driving unit of the (n+1)-th level, the drain of the third controllable transistor outputs the second control signals; and

the gate of the third controllable transistor of the GOA driving unit of the n-th level and the gate of the third controllable transistor of the GOA driving unit of the (n+1)-th level are interconnected.