Dynamic substrate biasing for extended voltage operation

• US 10,242,979 B1
• Filed: 06/26/2018
• Issued: 03/26/2019
• Est. Priority Date: 06/26/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Edwards, Willliam Ernest
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US16/018,958
• Time in Patent Office: 273 Days
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/0292 using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
• CPC Class Codes: H01L 27/0296 involving a specific disposition of the protective devices
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H02H 9/046 : responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

A device includes an integrated circuit (IC) layer, an insulative layer such as a buried oxide (BOX) layer, a substrate layer separated from the IC layer by the insulative layer, and a set of protective components such as a set of Zener diodes or a Zener stack coupled to the IC layer to protect the IC layer from transient electric events such as an electrostatic discharge (ESD), an inductive flyback, and a back electromotive force (back-EMF) event. The Zener stack has a Zener breakdown voltage greater than a breakdown voltage of the IC layer. An effective bias voltage has a voltage level less than the breakdown voltage of the IC layer. The Zener diode or Zener stack may be coupled to one or more isolation structures of the IC layer. The isolation structures separate the IC layer into electrically distinct portions or wells in which other electric components are formed.

Claims

1. A biased substrate circuit comprising:

an integrated circuit (IC) layer divided into wells by dielectric isolation regions of a dielectric isolation material, the dielectric isolation material having a first breakdown voltage;

a base substrate layer separated from the IC layer by an insulation layer having a second breakdown voltage; and

a voltage protection stack coupled to the base substrate layer in at least two different locations, the voltage protection stack including a plurality of voltage protection components, the voltage protection stack having a stack breakdown voltage greater than the first breakdown voltage and the second breakdown voltage.

2. The biased substrate circuit of claim 1, wherein:

the voltage protection stack has a stack voltage level;

each well of the IC layer has a breakdown voltage level; and

when the stack voltage level is exceeded, an applied voltage is divided across multiple wells of the IC layer such that a voltage level across any single well'"'"'s dielectric isolation is less than the well'"'"'s breakdown voltage level.

3. The biased substrate circuit of claim 1, wherein the biased substrate circuit is positioned at a corner or edge of a die that includes the IC layer.

4. The biased substrate circuit of claim 1, further comprising:

an edge seal along a periphery of the IC layer without a ground contact connecting the IC layer to ground.

5. The substrate biasing circuit of claim 1, further comprising:

a non-conductive epoxy layer coupled to the base layer.

6. The substrate biasing circuit of claim 1, wherein the base layer is 10 mils or less in thickness at a first point in the IC layer.

7. A device comprising:

a substrate layer separated by a buried oxide (BOX) layer, having a BOX isolation breakdown voltage, from an integrated circuit (IC) layer, the IC layer having IC components;

at least a first isolation structure disposed proximate to the IC layer, the first isolation structure extending through the BOX layer at least to the substrate layer, and the first isolation structure having an isolation breakdown voltage, the first isolation structure isolating the IC components; and

a protective stack having a stack breakdown voltage greater than the isolation breakdown voltage, the stack coupled to the substrate layer in at least two different locations, the stack comprising;

a first voltage protection component having a first anode coupled to one of the at least two different locations and a first cathode coupled to the first isolation structure and operable in use to receive a transient voltage, a difference between the transient voltage at a cathode of the stack and the substrate bias voltage being less than the isolation breakdown voltage; and

a second voltage protection component having a second anode and a second cathode, the second anode coupled to the first cathode of the first voltage protection component, the second cathode of the second voltage protection component being at the cathode of the stack.

8. The device of claim 7, wherein one of the at least two different locations is a ground.

9. The device of claim 7, further comprising:

a second isolation structure in the IC layer, the second isolation structure extending through the BOX layer at least to the substrate layer, and the second isolation structure coupled to ground, the first and second isolation structures defining a well of IC material.

10. The device of claim 9, wherein the first and the second isolation structures comprise a deep trench isolation (DTI) material.

11. The device of claim 7, wherein:

the substrate layer is N- doped;

or

the well of IC material is doped with an N-based doping material.

12. The device of claim 7, wherein the first voltage protection component includes a first Zener diode, and wherein the second voltage protection component includes a second Zener diode, and wherein each of the first and second voltage protection components has a breakdown voltage less than a breakdown voltage of the DTI material.

13. The device of claim 7, wherein IC components are formed in a well of IC material adjacent to an edge of the device and adjacent to the first isolation structure.

14. The device of claim 7, wherein:

the IC layer includes a plurality of wells of silicon-based IC material defined by a plurality of isolation structures, each isolation structure including a poly silicon material.

15. The device of claim 14, wherein:

a first well of the plurality of wells includes active IC components; and

a second well of the plurality of wells is devoid of any active IC components, the second well electrically isolating the first well from ground.

16. The device of claim 7, wherein the BOX layer is formed with an asymmetric breakdown voltage with respect to a voltage of a first voltage domain in the IC layer, the first voltage domain couplable to a first voltage source for operation of the IC components in the IC layer.

17. An electronic device comprising:

a voltage protection stack including a plurality of voltage protection components, wherein an anode of at least one of the voltage protection components is grounded, wherein a cathode of at least one of the voltage protection components is coupled to a load, the voltage protection stack having a stack breakdown voltage;

an integrated circuit (IC) layer having an IC layer breakdown voltage, the IC layer including;

active IC components, the IC layer coupled to a first voltage source of a first voltage level for operation of the active IC components; and

a first poly silicon region coupled to a cathode of at least one of the voltage protection components of the voltage protection stack;

an insulator layer having a first side adjacent to the IC layer; and

a substrate layer adjacent to a second side of the insulator layer, wherein the voltage protection stack breakdown voltage of the voltage protection stack is greater than the IC layer breakdown voltage.

18. The electronic device of claim 17, further comprising:

a first voltage source configured to provide a first voltage level; and

a second voltage source configured to provide a second voltage level to the IC layer for operation of the active IC components in the IC layer, the second voltage level different from the first voltage level.

19. The electronic device of claim 17, further comprising:

a capacitor coupled in parallel with the voltage protection stack between the first voltage source and the second voltage source, and wherein at least one of the voltage protection components includes a Zener diode.

20. The electronic device of claim 17, wherein:

the IC layer further includes a second poly silicon region coupled to ground; and

a trench isolation structure separates the IC layer from the first and the second poly silicon regions.