Semiconductor device and manufacturing method thereof

• US 10,243,005 B2
• Filed: 09/15/2016
• Issued: 03/26/2019
• Est. Priority Date: 08/07/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakata, Junichiro, Sakakura, Masayuki, Oikawa, Yoshiaki, Okazaki, Kenichi, Maruyama, Hotaka
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Liu, Benjamin T
• Application Number:
  US15/265,932
• Publication Number:
  US 20170005118A1
• Time in Patent Office: 922 Days
• CPC Class Codes: H01L 21/385 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0041 characterised by field-effect operation

Abstract

An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.

Claims

1. A semiconductor device comprising:

a driver circuit portion and a pixel portion each comprising;

a gate electrode layer; and

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping the gate electrode layer;

a first conductive layer over the oxide semiconductor layer, the first conductive layer being electrically connected to the oxide semiconductor layer;

a second conductive layer over the oxide semiconductor layer, the second conductive layer being electrically connected to the oxide semiconductor layer;

an oxide insulating layer over the oxide semiconductor layer, the first conductive layer and the second conductive layer, the oxide insulating layer being in contact with a first end portion of the oxide semiconductor layer and a second end portion of the oxide semiconductor layer; and

a terminal portion comprising;

a second oxide semiconductor layer; and

a fourth conductive layer,

wherein the pixel portion comprises a pixel electrode layer over the oxide insulating layer,

wherein the driver circuit portion comprises a third conductive layer which overlaps with the oxide semiconductor layer over the oxide insulating layer,

wherein the third conductive layer is not provided over the gate electrode layer of the pixel portion,

wherein the second conductive layer of the pixel portion is electrically connected to the pixel electrode layer, and

wherein an end portion of the second oxide semiconductor layer protrudes from an end portion of the fourth conductive layer.

2. The semiconductor device according to claim 1, wherein each of the pixel electrode layer and the third conductive layer is formed from a same conductive film.

3. The semiconductor device according to claim 1,

wherein each of the pixel electrode layer and the third conductive layer comprises an indium oxide-zinc oxide alloy.

4. The semiconductor device according to claim 1, wherein the third conductive layer is configured to be a gate electrode.

5. The semiconductor device according to claim 1, wherein the third conductive layer and the gate electrode of the driver circuit portion have a same potential.

6. The semiconductor device according to claim 1, wherein the third conductive layer is in a floating state.

7. The semiconductor device according to claim 1,

wherein the gate insulating layer has a single-layer structure or a stacked-layer structure of a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer.

8. The semiconductor device according to claim 1, wherein a peak of water at 300°

C. is not detected when a TDS (Thermal Desorption Spectroscopy) is performed on the oxide semiconductor layer.

9. A semiconductor device comprising:

a driver circuit portion and a pixel portion each comprising;

a gate electrode layer; and

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping the gate electrode layer;

a first conductive layer over the oxide semiconductor layer, the first conductive layer being electrically connected to the oxide semiconductor layer;

a second conductive layer over the oxide semiconductor layer, the second conductive layer being electrically connected to the oxide semiconductor layer;

an oxide insulating layer over the oxide semiconductor layer, the first conductive layer and the second conductive layer, the oxide insulating layer being in contact with a first end portion of the oxide semiconductor layer and a second end portion of the oxide semiconductor layer; and

a terminal portion comprising;

a second oxide semiconductor layer; and

a fourth conductive layer,

wherein the pixel portion comprises a pixel electrode layer over the oxide insulating layer,

wherein the driver circuit portion comprises a third conductive layer which overlaps with the oxide semiconductor layer over the oxide insulating layer,

wherein the third conductive layer is not provided over the gate electrode layer of the pixel portion,

wherein the second conductive layer of the pixel portion is electrically connected to the pixel electrode layer,

wherein the oxide insulating layer includes a region in an oxygen-excess state,

wherein oxygen in the region in the oxygen-excess state is diffused into the oxide semiconductor layer through a heat treatment, and

wherein an end portion of the second oxide semiconductor layer protrudes from an end portion of the fourth conductive layer.

10. The semiconductor device according to claim 9, wherein each of the pixel electrode layer and the third conductive layer is formed from a same conductive film.

11. The semiconductor device according to claim 9,

wherein each of the pixel electrode layer and the third conductive layer comprises an indium oxide-zinc oxide alloy.

12. The semiconductor device according to claim 9, wherein the third conductive layer is configured to be a gate electrode.

13. The semiconductor device according to claim 9, wherein the third conductive layer and the gate electrode of the driver circuit portion have a same potential.

14. The semiconductor device according to claim 9, wherein the third conductive layer is in a floating state.

15. The semiconductor device according to claim 9,

wherein the gate insulating layer has a single-layer structure or a stacked-layer structure of a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer.

16. The semiconductor device according to claim 9, wherein a peak of water at 300°

C. is not detected when a TDS (Thermal Desorption Spectroscopy) is performed on the oxide semiconductor layer.