System, device, and method for controlling a power inverter

• US 10,243,407 B2
• Filed: 10/31/2016
• Issued: 03/26/2019
• Est. Priority Date: 10/04/2016
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Inventors: Vladan, Marius Ionel, Hoste, Steve, Koleck, Jean-Francois
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US15/338,566
• Publication Number:
  US 20180097400A1
• Time in Patent Office: 876 Days
• Field of Search: 307104
• CPC Class Codes: H02J 50/12 of the resonant type

Abstract

A wireless power transmitter includes circuitry configured to determine a reflected impedance from a receiver coil at a transmitter coil and control a dead-time of one or more switching stages of a power conversion device based on the reflected impedance. A tunable matching network at the transmitter is controlled based on the reflected impedance and the dead-time of the one or more switching stages.

Claims

1. A device comprising:

circuitry configured to

determine a load impedance for at least one power conversion device,

control a dead-time of one or more switching stages of the at least one power conversion device based on the load impedance,

control a tunable matching network based on the load impedance and the dead-time of the one or more switching stages, and

modify the dead-time of the one or more switching stages including a plurality of switches based on a comparator output indicating an amount of body diode conduction of the plurality of switches.

2. The device of claim 1, wherein the circuitry is further configured to determine the load impedance based on at least one of a supply voltage for the one or more switching stages, a peak current through the one or more switching stages, a current at a transmitter coil, or a junction temperature of the one or more switching stages.

3. The device of claim 1, wherein the power conversion device is a half-bridge DC-AC power inverter.

4. The device of claim 1, wherein the tunable matching network is in series or in parallel with the load.

5. The device of claim 1, wherein the circuitry is further configured to determine an impedance of the tunable matching network resulting in a total impedance of the load impedance and the impedance of the tunable matching network that corresponds to a predetermined operational efficiency range of the power conversion device.

6. The device of claim 1, wherein a total impedance of the one or more switching stages is inductive.

7. The device of claim 1, wherein the one or more switching stages include a first switch and a second switch, and the circuitry is configured to modify the dead-time based on a comparator output indicating an amount of body diode conduction of the first switch and the second switch.

8. The device of claim 7, wherein the comparator is configured to compare a voltage at a common connection point between the first switch and the second switch to a threshold voltage, wherein the comparator is configured to

output a first signal in response to determining that the voltage at the common connection point is less than the threshold voltage;

and

output a second signal in response to determining that the voltage at the common connection point is greater than the threshold voltage.

9. The device of claim 7, wherein the circuitry further includes a first digital accumulator and a second digital accumulator configured to calculate an average of the comparator output based on outputs from one or more latch circuits.

10. The device of claim 9, wherein the first digital accumulator is configured to detect first variations in the amount of body diode conduction in a case that the first switch is turned off and the second switch is turned on;

and

the second digital accumulator is configured to detect second variations in the amount of body diode conduction in a case that the first switch is turned on and the second switch is turned off.

11. The device of claim 9, wherein the circuitry is further configured to reduce the dead-time between the first switch and the second switch in response to determining that a first value of the first digital accumulator or a second value of the second digital accumulator is greater than a first accumulator threshold.

12. The device of claim 11, wherein the circuitry is further configured to increase the dead-time between the first switch and the second switch in response to determining that the first value of the first digital accumulator or the second value of the second digital accumulator is less than a second accumulator threshold that is less than the first accumulator threshold.

13. The device of claim 9, wherein the circuitry is further configured to modify an impedance of the tunable matching network in response to determining that a second value of the second digital accumulator is greater than zero resulting in a reactance of a switching stage load becoming more inductive.

14. The device of claim 9, wherein the circuitry is further configured to modify an impedance of the tunable matching network in response to determining that a first value of the first digital accumulator and a second value of the second digital accumulator are equal to zero resulting in a reactance of a switching stage load becoming more inductive.

15. The device of claim 9, wherein the circuitry is further configured to control the dead-time between the first switch and the second switch within a predetermined dead-time range having an upper dead-time threshold and a lower dead-time threshold.

16. The device of claim 15, wherein the circuitry is further configured to modify an impedance of the tunable matching network in response to determining that a first value of a first accumulator is greater than zero and the dead-time between the first switch and the second switch is greater than or equal to the upper dead-time threshold.

17. The device of claim 16, wherein the circuitry is further configured to modify an impedance of the tunable matching network in response to determining that a first value of a first accumulator is greater than zero and the dead-time between the first switch and the second switch is less than or equal to the lower dead-time threshold.

18. The device of claim 1, wherein the circuitry is further configured to control the dead-time of the one or more switching stages by modifying one or more delay signals corresponding to control signals for the one or more switching stages.

19. A method comprising:

determining a reflected impedance from a receiver coil at a coil of a wireless power transmitter;

controlling a dead-time of one or more switching stages of at least one power conversion device of the wireless power transmitter based on the reflected impedance;

controlling an impedance of a tunable matching network based on the reflected impedance and the dead-time of the one or more switching stages; and

modifying the dead-time of the one or more switching stages including a plurality of switches based on a comparator output indicating an amount of body diode conduction of the plurality of switches.

20. A wireless power transmitter comprising:

circuitry configured to

determine a reflected impedance from a receiver coil at a transmitter coil,

control a dead-time of one or more switching stages of a power conversion device based on the reflected impedance,

control a tunable impedance of a matching network at the transmitter based on the reflected impedance and the dead-time of the one or more switching stages, and

modify the dead-time of the one or more switching stages including a plurality of switches based on a comparator output indicating an amount of body diode conduction of the plurality of switches.