Semiconductor device and display device comprising oxide semiconductor layer

• US 10,249,647 B2
• Filed: 07/23/2015
• Issued: 04/02/2019
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Miyake, Hiroyuki
• Primary Examiner(s): Bradley, Stephen M
• Application Number:
  US14/807,168
• Publication Number:
  US 20150333089A1
• Time in Patent Office: 1,349 Days
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer;

an oxide semiconductor layer comprising a channel formation region adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium; and

source and drain electrode layers in electrical contact with the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises a crystalline region including a crystal with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, and

wherein a c-axis of the crystal is oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

2. The semiconductor device according to claim 1,

wherein each of the gate electrode layer and the source and drain electrode layers is a conductive layer having a light transmitting property.

3. The semiconductor device according to claim 1,

wherein the gate electrode layer is located over the oxide semiconductor layer.

4. The semiconductor device according to claim 1,

wherein the gate electrode layer is located under the oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises gallium and zinc.

6. The semiconductor device according to claim 1,

wherein the source and drain electrode layers comprise titanium, and

wherein the semiconductor device further comprises a titanium oxide layer between the oxide semiconductor layer and at least one of the source and drain electrode layers.

7. The semiconductor device according to claim 1,

wherein the source and drain electrode layers comprise an element selected from chromium, tantalum, titanium, molybdenum, tungsten, and a combination thereof.

8. The semiconductor device according to claim 1,

wherein a donor concentration of the channel formation region is lower than or equal to 1×

10¹⁸/cm³.

9. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer;

an oxide semiconductor layer comprising a channel formation region adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium, and

source and drain electrode layers in electrical contact with the oxide semiconductor layer;

wherein the oxide semiconductor layer comprises a first crystalline region including a crystal whose c-axis is oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer in a superficial portion of the oxide semiconductor layer and a second crystalline region including microcrystals, and

wherein a grain diameter of the crystal in the first crystalline region is greater than or equal to 1 nm and less than or equal to 20 nm.

10. The semiconductor device according to claim 9,

wherein each of the gate electrode layer and the source and drain electrode layers is a conductive layer having a light transmitting property.

11. The semiconductor device according to claim 9,

wherein the gate electrode layer is located over the oxide semiconductor layer.

12. The semiconductor device according to claim 9,

wherein the gate electrode layer is located under the oxide semiconductor layer.

13. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer comprises gallium and zinc.

14. The semiconductor device according to claim 9,

wherein the source and drain electrode layers comprise titanium, and

wherein the semiconductor device further comprises a titanium oxide layer between the oxide semiconductor layer and at least one of the source and drain electrode layers.

15. The semiconductor device according to claim 9,

wherein the source and drain electrode layers comprise an element selected from chromium, tantalum, titanium, molybdenum, tungsten, and a combination thereof.

16. The semiconductor device according to claim 9,

wherein a donor concentration of the channel formation region is lower than or equal to 1×

10¹⁸/cm³.

17. A display device comprising:

a pixel portion including a first transistor over a substrate,

wherein the first transistor comprises;

a first gate electrode layer;

a first gate insulating layer;

a first oxide semiconductor layer comprising a channel formation region adjacent to the first gate electrode layer with the first gate insulating layer therebetween, the first oxide semiconductor layer comprising indium; and

first source and drain electrode layers in electrical contact with the first oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a crystalline region with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, and

wherein the crystalline region in the first oxide semiconductor layer includes a crystal whose c-axis is oriented in a direction substantially perpendicular to a surface of the first oxide semiconductor layer.

18. The display device according to claim 17,

wherein each of the first gate electrode layer and the first source and drain electrode layers is a conductive layer having a light transmitting property.

19. The display device according to claim 17, further comprising:

a driver circuit portion including a second transistor over the substrate,

wherein the second transistor comprises;

a second gate electrode layer;

a second gate insulating layer;

a second oxide semiconductor layer comprising a channel formation region adjacent to the second gate electrode layer with the second gate insulating layer therebetween; and

second source and drain electrode layers in electrical contact with the second oxide semiconductor layer,

wherein the second oxide semiconductor layer comprises a crystalline region with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, and

wherein the crystalline region in the second oxide semiconductor layer includes a crystal whose c-axis is oriented in a direction perpendicular to a surface of the second oxide semiconductor layer.

20. The display device according to claim 19,

wherein the first gate electrode layer is located under the first oxide semiconductor layer, and

wherein the second gate electrode layer is located over the second oxide semiconductor layer.