Fabrication method for thin film transistor, thin film transistor and display apparatus

• US 10,256,103 B2
• Filed: 03/10/2017
• Issued: 04/09/2019
• Est. Priority Date: 02/27/2017
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Wang, Wei
• Primary Examiner(s): Woldegeorgis, Ermias T
• Application Number:
  US15/546,711
• Publication Number:
  US 20180277376A1
• Time in Patent Office: 760 Days
• CPC Class Codes: H01L 21/3003 Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H10K 2102/311 Flexible OLED
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 77/111 Flexible substrates

Abstract

The present application discloses a method for fabricating a thin film transistor including the steps of: sequentially forming an active layer, a gate insulating layer, a gate, and a capacitive insulating layer on a substrate, the gate insulating layer isolating the active layer from the gate; a hydrogen-blocking layer is formed on the side of the capacitive insulating layer facing away from the substrate, and the hydrogen-blocking layer covering the capacitive insulating layer; and performing hydrogenation treatment to the gate insulating layer and the active layer. The present application also discloses a thin film transistor and a display apparatus. In improving the flexibility of the AMOLED display apparatus while ensuring the hydrogenation effect of the polysilicon thin film transistor, the fabricated thin film transistor has high electron mobility, and the display apparatus has a good display performance.

Claims

1. A method for fabricating a thin film transistor, comprising:

forming an active layer, a gate insulating layer, a gate, and a capacitive insulating layer sequentially on the substrate, the gate insulating layer isolating the active layer from the gate;

forming a hydrogen-blocking layer on the side of the capacitive insulating layer facing away from the substrate, and the hydrogen-blocking layer covering the capacitive insulating layer; and

performing hydrogenation treatment to the gate insulating layer and the active layer.

2. The method for fabricating a thin film transistor according to claim 1, wherein the temperature of the hydrogenation treatment is not more than 500°

C. and the duration of the hydrogenation treatment is not more than 60 minutes.

3. The method for fabricating a thin film transistor according to claim 2, wherein the hydrogen-blocking layer is a conductive material, and after the step of performing hydrogenation treatment to the gate insulating layer and the active layer, the method further comprises:

patterning the hydrogen-blocking layer to form a capacitive upper electrode.

4. The method for fabricating a thin film transistor according to claim 2, wherein after the step of performing hydrogenation treatment to the gate insulating layer and the active layer, the method further comprises:

depositing a conductive material on a side of the surface of the hydrogen-blocking layer facing away from the substrate, and patterning the conductive material to form the capacitive upper electrode.

5. The method for fabricating a thin film transistor according to claim 3, wherein after forming the capacitive upper electrode, an interlayer insulating layer is formed on a side of the surface of the capacitive upper electrode facing away from the substrate, and a source and a drain are formed on the surface of the interlayer insulating layer.

6. The method for fabricating a thin film transistor according to claim 4, wherein after forming the capacitive upper electrode, an interlayer insulating layer is formed on a side of the surface of the capacitive upper electrode facing away from the substrate, and a source and a drain are formed on the surface of the interlayer insulating layer.

7. A thin film transistor, comprising:

a substrate and an active layer, a gate insulating layer, a gate, and a capacitive insulating layer sequentially formed on a side of the substrate, wherein the thin film transistor is a hydrogen-blocking layer, and the hydrogen-blocking layer is disposed on a side of the capacitive insulating layer facing away from the substrate, and covering the capacitive insulating layer; and

the hydrogen-blocking layer is for blocking the outwardly diffusion of the hydrogen ions provided by the capacitive insulating layer during the hydrogenation treatment.

8. The thin film transistor according to claim 7, wherein the thin film transistor further comprises a capacitive upper electrode, an interlayer insulating layer, a source, and a drain disposed on the side of the hydrogen-blocking layer facing away from the substrate, and the interlayer insulating layer isolates the capacitive upper electrode from the source and the drain on both sides of the interlayer insulating layer.

9. The thin film transistor according to claim 8, wherein the interlayer insulating layer is an organic material film layer.

10. The thin film transistor according to claim 7, wherein the hydrogen-blocking layer is an inorganic material film layer or a metal material film layer.

11. A display apparatus, comprising a thin film transistor, the thin film transistor comprising:

a substrate and an active layer, a gate insulating layer, a gate, and a capacitive insulating layer sequentially formed on a side of the substrate, wherein the thin film transistor further comprises a hydrogen-blocking layer, and the hydrogen-blocking layer is disposed on a side of the capacitive insulating layer facing away from the substrate, and covering the capacitive insulating layer; and

the hydrogen-blocking layer is for blocking the outwardly diffusion of the hydrogen ions provided by the capacitive insulating layer during the hydrogenation treatment.

12. The display apparatus according to claim 11, wherein the thin film transistor further comprises a capacitive upper electrode, an interlayer insulating layer, a source, and a drain disposed on the side of the hydrogen-blocking layer facing away from the substrate, and the interlayer insulating layer isolates the capacitive upper electrode from the source and the drain on both sides of the interlayer insulating layer.

13. The display apparatus according to claim 12, wherein the interlayer insulating layer is an organic material film layer.

14. The display apparatus according to claim 11, wherein the hydrogen-blocking layer is an inorganic material film layer or a metal material film layer.