Microcontroller programmable system on a chip

• US 10,261,932 B2
• Filed: 03/10/2017
• Issued: 04/16/2019
• Est. Priority Date: 10/26/2000
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren S., Mar, Monte
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US15/455,393
• Publication Number:
  US 20170185558A1
• Time in Patent Office: 767 Days
• Field of Search: None
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25033 structure, control, syncronization, data, alarm, connect I-O line to interface
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Claims

1. A microcontroller comprising:

a plurality of programmable analog circuit blocks;

a plurality of programmable digital circuit blocks;

a programmable interconnect coupling the analog circuit blocks and the digital circuit blocks; and

a bus coupling analog input/output data and digital input/output data for the analog circuit blocks and the digital circuit blocks.

2. A microcontroller according to claim 1 wherein one of the digital circuit blocks is configured to implement logical operations.

3. A microcontroller according to claim 1 wherein one of the digital circuit blocks is configured to implement computational operations.

4. A microcontroller according to claim 1 wherein the programmable interconnect structure and the programmable analog circuit blocks and the plurality of programmable digital circuit blocks are constructed on a semiconductor chip.

5. A microcontroller according to claim 1 wherein the programmable analog circuit blocks comprise at least one continuous time analog circuit block.

6. A microcontroller according to claim 1 wherein the programmable analog circuit blocks comprise at least one switched capacitor analog circuit block.

7. A microcontroller according to claim 1 wherein the programmable digital circuit blocks comprise at least one digital multi-function circuit block having a first set of digital functions and at least one digital multi-function circuit block having a second set of digital functions different from the first set.

8. A method of providing a dynamically programmable analog/digital communication interface circuit, comprising:

configuring a plurality of programmable analog circuit blocks to implement at least one of a plurality of analog functions,

configuring a plurality of programmable digital circuit blocks to implement at least one of a plurality of digital functions; and

configuring a routing matrix to couple analog data and digital data between the programmable analog circuit blocks and the programmable digital circuit blocks.

9. The method according to claim 8 wherein flash memory is used to program the routing matrix and the plurality of programmable analog circuit blocks and the plurality of programmable digital circuit blocks and to enable dynamic circuit reconfiguration.

10. The method according to claim 8 wherein the programmable analog circuit blocks comprise at least one continuous time analog circuit and at least one switched capacitor analog circuit.

11. The method according to claim 8 wherein the programmable digital circuit blocks comprise at least one standard digital multi-function circuit having a first set of digital functions and at least one enhanced digital multi-function circuit having at least one function differing from the first set of digital functions.

12. The method according to claim 8 wherein the programmable analog circuit blocks comprise at least one multi-function circuit programmable for at least one of the plurality of analog functions and at least one fixed function circuit programmable for a fixed function with at least one of a number of different parameters.

13. The method according to claim 8 wherein the plurality of digital functions comprises logical operations.

14. The method according to claim 8 wherein the plurality of digital functions comprises computational operations.