Radio frequency switch

• US 10,263,616 B1
• Filed: 03/29/2018
• Issued: 04/16/2019
• Est. Priority Date: 03/29/2018
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Scott, Baker, Maxim, George, Leipold, Dirk Robert Walter
• Primary Examiner(s): Zweizig, Jeffery S
• Application Number:
  US15/939,625
• Time in Patent Office: 383 Days
• Field of Search: None
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/40 Circuits

Abstract

A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells is made up of a main field-effect transistor (FET) having a main drain terminal, a main source terminal, a main gate terminal, and a main body terminal. Further included is a first body bias FET having a first drain terminal coupled to the main gate terminal, a first gate terminal coupled to the main drain terminal, a first body terminal coupled to the main body terminal, and a first source terminal, and a second body bias FET having a second drain terminal coupled to the main gate terminal, a second body terminal coupled to the main body terminal, and a second source terminal coupled to the first source terminal.

Claims

1. A radio frequency switch comprising a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node wherein each of the plurality of switch cells comprises:

a main field-effect transistor (FET) comprising a main drain terminal, a main source terminal, a main gate terminal, and a main body terminal; and

an off-state linearization network comprising;

a first body bias FET having a first drain terminal coupled to the main gate terminal, a first gate terminal coupled to the main drain terminal, a first body terminal coupled to the main body terminal, and a first source terminal; and

a second body bias FET having a second drain terminal coupled to the main gate terminal, a second body terminal coupled to the main body terminal, and a second source terminal coupled to the first source terminal.

2. The radio frequency switch of claim 1 wherein the main body terminal is coupled to the first source terminal and the second source terminal.

3. The radio frequency switch of claim 1 wherein the first body bias FET and the second body bias FET are n-type FET devices.

4. The radio frequency switch of claim 1 wherein the first body bias FET and the second body bias FET share a body diffusion with the main FET.

5. The radio frequency switch of claim 1 wherein the first body bias FET and the second body bias FET have body diffusions that are separate from a body diffusion of the main FET.

6. The radio frequency switch of claim 1 wherein the main FET is at least 1000 times larger than either of the first body bias FET or the second body bias FET.

7. The radio frequency switch of claim 1 wherein the main FET is from 1000 times larger to 3000 times larger than either of the first body bias FET or the second body bias FET.

8. The radio frequency switch of claim 1 wherein the main FET is from 3000 times larger to 6000 times larger than either of the first body bias FET or the second body bias FET.

9. The radio frequency switch of claim 1 wherein the main FET, the first body bias FET, and the second body bias FET are inversion-type FET devices.

10. The radio frequency switch of claim 1 further including gate resistors, one for each of the plurality of switch cells, wherein the gate resistors are coupled between a gate control terminal common to the plurality of switch cells and the main gate terminal of each of the plurality of switch cells.

11. A radio frequency switch cell comprising:

a main field-effect transistor (FET) comprising a main drain terminal, a main source terminal, a main gate terminal, and a main body terminal; and

an off-state linearization network comprising;

a first body bias FET having a first drain terminal coupled to the main gate terminal, a first gate terminal coupled to the main drain terminal, a first body terminal coupled to the main body terminal, and a first source terminal; and

a second body bias FET having a second drain terminal coupled to the main gate terminal, a second body terminal coupled to the main body terminal, and a second source terminal coupled to the first source terminal.

12. The radio frequency switch cell of claim 11 wherein the main body terminal is coupled to the first source terminal and the second source terminal.

13. The radio frequency switch cell of claim 11 wherein the first body bias FET and the second body bias FET are n-type FET devices.

14. The radio frequency switch cell of claim 11 wherein the first body bias FET and the second body bias FET share a body diffusion with the main FET.

15. The radio frequency switch cell of claim 11 wherein the first body bias FET and the second body bias FET have body diffusions that are separate from a body diffusion of the main FET.

16. The radio frequency switch cell of claim 11 wherein the main FET is at least 1000 times larger than either of the first body bias FET or the second body bias FET.

17. The radio frequency switch cell of claim 11 wherein the main FET is from 1000 times larger to 3000 times larger than either of the first body bias FET or the second body bias FET.

18. The radio frequency switch cell of claim 11 wherein the main FET is from 3000 times larger to 6000 times larger than either of the first body bias FET or the second body bias FET.

19. The radio frequency switch cell of claim 11 wherein the main FET, the first body bias FET, and the second body bias FET are inversion-type FET devices.

20. The radio frequency switch cell of claim 11 further including a gate resistor coupled between a gate control terminal and the main gate terminal.