Semiconductor package and a method of manufacturing the same

• US 10,269,677 B2
• Filed: 04/19/2017
• Issued: 04/23/2019
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Choi, Jae Sik, Oh, Dong Seong, Go, Si Hyeon
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Isaac, Stanetta D
• Application Number:
  US15/491,025
• Publication Number:
  US 20180151465A1
• Time in Patent Office: 734 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent

Abstract

A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.

Claims

1. A method to manufacture a semiconductor package, the method comprising:

preparing a metal substrate;

attaching semiconductor dies to a first side of the metal substrate, the attached semiconductor dies being spaced apart from each other;

attaching a bonding film to the semiconductor dies;

applying a mold material in areas between the attached semiconductor dies and on a second side of the metal substrate, and curing the mold material to form a mold member;

grinding the mold member formed on the second side of the metal substrate and a part of the metal substrate;

removing the bonding film;

attaching a redistribution layer to the semiconductor dies; and

cutting between the semiconductor dies.

2. The method of claim 1, wherein the attaching of the semiconductor dies comprises:

applying an adhesive conductive material on the first side of the metal substrate, and

attaching the semiconductor dies to the first side of the metal substrate with the adhesive conductive material.

3. The method of claim 1, wherein the preparing of the metal substrate comprises etching portions of the metal substrate on the first or second side of the metal substrate to a depth to define an array of rectangular-shaped portions on the first or second side of the metal substrate.

4. The method of claim 3, wherein the attaching of the semiconductor dies comprises attaching the semiconductor dies to the rectangular-shaped portions of the metal substrate on the first side of the metal substrate.

5. The method of claim 3, wherein the attaching of the semiconductor dies comprises attaching the semiconductor dies to portions of the metal substrate corresponding to the rectangular-shaped portions on the second side of the metal substrate.

6. The method of claim 5, further comprising:

plating an intermediate product formed by the attaching of the redistribution layer.

7. The method of claim 6, further comprising:

marking product information on the metal substrate after the plating of the intermediate product.

8. The method of claim 1, wherein the grinding of the part of the metal substrate comprises grinding the metal substrate until the semiconductor dies are electrically separated.

9. The method of claim 1, wherein the metal substrate comprises a copper substrate.

10. The method of claim 1, wherein the preparing of the metal substrate comprises etching portions of the second side of the metal substrate to form recessed areas on the second side of the metal substrate,

wherein the forming of the mold member comprises forming the mold member in the recessed areas, and

wherein the grinding of the mold member formed on the second side of the metal substrate comprises grinding the mold member until a plurality of mold member portions spaced apart from each other are formed in the recessed areas.

11. A method to manufacture a semiconductor package, the method comprising:

attaching semiconductor dies to a first side of a metal substrate so that the semiconductor dies are spaced apart on the first side;

forming a mold member in areas between the attached semiconductor dies and on a second side of the metal substrate;

grinding the mold member formed on the second side of the metal substrate and a part of the metal substrate to reduce a thickness of the mold member and the metal substrate;

attaching a redistribution layer to the semiconductor dies; and

cutting in an area between adjacent semiconductor dies among the semiconductor dies to separate the adjacent semiconductor dies.

12. The method of claim 11, further comprising:

etching the first side of the metal substrate to form recessed areas in the first side of the metal substrate prior to the forming of the mold member,

wherein the forming of the mold member in the areas between the attached semiconductor dies and on the second side of the metal substrate comprises forming the mold member in the recessed areas.

13. The method of claim 12, wherein the grinding of the mold member on the second side of the metal substrate and the metal substrate comprises grinding the mold member on the second side of the metal substrate and the metal substrate so that the semiconductor dies are electrically separated from each other.

14. The method of claim 11, further comprising:

etching the second side of the metal substrate, which is disposed opposite to the first side, to form recessed areas in the second side prior to the forming of the mold member,

wherein the forming of the mold member in the areas between the attached semiconductor dies and on the second side of the metal substrate comprises forming the mold member in the recessed areas.

15. The method of claim 14, wherein the grinding of the mold member on the second side of the metal substrate and the metal substrate comprises grinding the mold member on the second side of the metal substrate and the metal substrate so that the semiconductor dies are electrically connected to each other by the metal substrate.