Method of manufacturing lower temperature polycrystal silicon thin film transistor array substrate

• US 10,269,974 B2
• Filed: 04/30/2015
• Issued: 04/23/2019
• Est. Priority Date: 03/16/2015
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Lu, Macai
• Primary Examiner(s): Smith, Bradley
• Assistant Examiner(s): Goodwin, David J
• Application Number:
  US14/888,645
• Publication Number:
  US 20180122957A1
• Time in Patent Office: 1,454 Days
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

The present invention discloses a method of manufacturing array substrate, comprising: A) defining a heavily doped region and a lightly doped region of a source electrode of an N-channel area, and a heavily doped region and a lightly doped region of a drain electrode of the N-channel area by using a first photomask having a first pattern; B) defining a doped region of a source electrode of a P-channel area and a doped region of a drain electrode of the P-channel area by using a second photomask having a second pattern; C) defining a pixel region, a contact hole region by using a third photomask having a third pattern; and D) defining a metal electrode region by using a fourth photomask having a fourth pattern.

Claims

1. A method of manufacturing lower temperature polycrystal silicon thin film transistor array substrate, comprising:

A) defining a heavily doped region of a source electrode of an N-channel area, a lightly doped region of the source electrode of the N-channel area, a heavily doped region of a drain electrode of the N-channel area and a lightly doped region of the drain electrode of the N-channel area by using a first photomask having a first pattern;

B) defining a doped region of a source electrode of a P-channel area and a doped region of a drain electrode of the P-channel area by using a second photomask having a second pattern;

C) defining a pixel region, a contact hole region at the heavily doped region of the drain electrode of the N-channel area, a contact hole region at the heavily doped region of the source electrode of the N-channel area, a contact hole region at the heavily doped region of the drain electrode of the P-channel area, and a contact hole region at the heavily doped region of the source electrode of the P-channel area by using a third photomask having a third pattern; and

D) defining a metal electrode region at the heavily doped region of the drain electrode of the N-channel area, a metal electrode region at the heavily doped region of the source electrode of the N-channel area, a metal electrode region at the heavily doped region of the drain electrode of the P-channel area, and a metal electrode region at the heavily doped region of the source electrode of the P-channel area by using a fourth photomask having a fourth pattern;

wherein step B) further comprises;

coating a photoresist on a substrate after performing said step A);

exposing and developing the photoresist by using the second photomask, so as to remove the photoresist between the N-channel area and the P-channel area, and to remove part of the photoresist above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area;

removing a polycrystal silicon layer, a first insulating layer and a first metal layer between the N-channel area and the P-channel area;

removing remaining photoresist above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area;

etching and removing the first metal layer above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area;

performing ion implantation on the doped region of the source electrode of the P-channel area and the doped region of the drain electrode of the P-channel area; and

removing all remaining photoresist.

2. The method of claim 1, wherein the first photomask is a greyscale photomask or a halftone photomask.

3. The method of claim 1, wherein the second photomask is a greyscale photomask or a halftone photomask.

4. The method of claim 1, wherein the third photomask is a greyscale photomask or a halftone photomask.

5. The method of claim 1, wherein the fourth photomask is a greyscale photomask or a halftone photomask.

6. The method of claim 1, wherein step A) further comprises:

forming in sequence a buffer layer, the polycrystal silicon layer, the first insulating layer and the first metal layer on the substrate;

coating a layer of the photoresist on the first metal layer;

exposing and developing the photoresist by using the first photomask, so as to remove the photoresist above the heavily doped region of the source electrode of the N-channel area and above the heavily doped region of the drain electrode of the N-channel area, and to remove part of the photoresist above the lightly doped region of the source electrode and above the lightly doped region of the drain electrode;

etching and removing the first metal layer above the heavily doped region of the source electrode of the N-channel area and above the heavily doped region of the drain electrode of the N-channel area;

performing a first ion implantation on the heavily doped region of the source electrode of the N-channel area and the heavily doped region of the drain electrode of the N-channel area;

removing remaining photoresist above the lightly doped region of the source electrode of the N-channel area and above the lightly doped region of the drain electrode of the N-channel area;

etching and removing the first metal layer above the lightly doped region of the source electrode and the lightly doped region of the drain electrode;

performing a second ion implantation again on the heavily doped region and lightly doped region of the source electrode of the N-channel area as well as the heavily doped region and lightly doped region of the drain electrode of the N-channel area; and

removing all remaining photoresist.

7. The method of claim 2, wherein step A) further comprises:

forming in sequence a buffer layer, the polycrystal silicon layer, the first insulating layer and the first metal layer on the substrate;

coating a layer of the photoresist on the first metal layer;

exposing and developing the photoresist by using the first photomask, so as to remove the photoresist above the heavily doped region of the source electrode of the N-channel area and above the heavily doped region of the drain electrode of the N-channel area, and to remove part of the photoresist above the lightly doped region of the source electrode and above the lightly doped region of the drain electrode;

etching and removing the first metal layer above the heavily doped region of the source electrode of the N-channel area and above the heavily doped region of the drain electrode of the N-channel area;

performing a first ion implantation on the heavily doped region of the source electrode of the N-channel area and the heavily doped region of the drain electrode of the N-channel area;

removing remaining photoresist above the lightly doped region of the source electrode of the N-channel area and above the lightly doped region of the drain electrode of the N-channel area;

etching and removing the first metal layer above the lightly doped region of the source electrode and the lightly doped region of the drain electrode;

performing a second ion implantation again on the heavily doped region and lightly doped region of the source electrode of the N-channel area as well as the heavily doped region and lightly doped region of the drain electrode of the N-channel area; and

removing all remaining photoresist.

8. The method of claim 1, wherein the step C) comprises:

forming a second insulating layer, a transparent conductive layer and the photoresist on the substrate after finishing step B);

exposing and developing the photoresist by using the third photomask, so as to remove the photoresist above the heavily doped region of the drain electrode of the N-channel area and above the heavily doped region of the source electrode of the N-channel area, and to remove the photoresist above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area;

removing the first insulating layer, the transparent conductive layer and the second insulating layer above the heavily doped region of the drain electrode of the N-channel area and above the heavily doped region of the source electrode of the N-channel area, as well as above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area, so as to form a contact hole;

removing all photoresist except the photoresist in the pixel region, so as to expose all the other transparent conductive layer than the transparent conductive layer in said pixel region; and

removing the exposed transparent conductive layer.

9. The method of claim 4, wherein the step C) comprises:

forming a second insulating layer, a transparent conductive layer and the photoresist on the substrate after finishing step B);

exposing and developing the photoresist by using the third photomask, so as to remove the photoresist above the heavily doped region of the drain electrode of the N-channel area and above the heavily doped region of the source electrode of the N-channel area, and to remove the photoresist above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area;

removing the first insulating layer, the transparent conductive layer and the second insulating layer above the heavily doped region of the drain electrode of the N-channel area and above the heavily doped region of the source electrode of the N-channel area, as well as above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area, so as to form a contact hole;

removing all photoresist except the photoresist in the pixel region, so as to expose all the other transparent conductive layer than the transparent conductive layer in said pixel region; and

removing the exposed transparent conductive layer.

10. The method of claim 1, wherein the step D) comprises:

forming a second metal layer on the substrate after finishing step C);

coating the photoresist on the second metal layer;

exposing and developing the photoresist by using the fourth photomask, so as to remove all photoresist except the photoresist above the heavily doped region of the drain electrode of the N-channel area and above the heavily doped region of the source electrode of the N-channel area, and the photoresist above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area;

etching and removing the exposed second metal layer;

removing the photoresist above the heavily doped region of the drain electrode of the N-channel area and the photoresist above doped region of the source electrode of the P-channel area;

removing part of the photoresist above the heavily doped region of the source electrode of the N-channel area and removing part of the photoresist above the doped region of the drain electrode of the P-channel area;

forming a passivation layer through deposition; and

removing part of the photoresist above the heavily doped region of the source electrode of the N-channel area and removing part of the photoresist and the passivation layer above the doped region of the drain electrode of the P-channel area.

11. The method of claim 5, wherein the step D) comprises:

forming a second metal layer on the substrate after finishing step C);

coating the photoresist on the second metal layer;

exposing and developing the photoresist by using the fourth photomask, so as to remove all photoresist except the photoresist above the heavily doped region of the drain electrode of the N-channel area and above the heavily doped region of the source electrode of the N-channel area, and the photoresist above the doped region of the source electrode of the P-channel area and above the doped region of the drain electrode of the P-channel area;

etching and removing the exposed second metal layer;

removing the photoresist above the heavily doped region of the drain electrode of the N-channel area and the photoresist above doped region of the source electrode of the P-channel area;

removing part of the photoresist above the heavily doped region of the source electrode of the N-channel area and removing part of the photoresist above the doped region of the drain electrode of the P-channel area;

forming a passivation layer through deposition; and

removing part of the photoresist above the heavily doped region of the source electrode of the N-channel area and removing part of the photoresist and the passivation layer above the doped region of the drain electrode of the P-channel area.