Configurable logic platform with multiple reconfigurable regions
First Claim
1. A configurable logic platform comprising:
- a physical interconnect for connecting the configurable logic platform to a processor;
a first reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the first reconfigurable logic region;
a second reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the second reconfigurable logic region;
a configuration port for applying the configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the configuration data corresponding to the second reconfigurable logic region;
a control plane function accessible via transactions of the physical interconnect, the control plane function in communication with the configuration port, the control plane function providing restricted access to the configuration port from the physical interconnect;
a first data plane function accessible via transactions of the physical interconnect, the first data plane function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect;
a second data plane function accessible via transactions of the physical interconnect, the second data plane function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect; and
arbitration logic configured to apportion bandwidth of the physical interconnect among at least the first data plane function and the second data plane function.
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Accused Products
Abstract
The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
38 Citations
20 Claims
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1. A configurable logic platform comprising:
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a physical interconnect for connecting the configurable logic platform to a processor; a first reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the first reconfigurable logic region; a second reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the second reconfigurable logic region; a configuration port for applying the configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the configuration data corresponding to the second reconfigurable logic region; a control plane function accessible via transactions of the physical interconnect, the control plane function in communication with the configuration port, the control plane function providing restricted access to the configuration port from the physical interconnect; a first data plane function accessible via transactions of the physical interconnect, the first data plane function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect; a second data plane function accessible via transactions of the physical interconnect, the second data plane function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect; and arbitration logic configured to apportion bandwidth of the physical interconnect among at least the first data plane function and the second data plane function. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A server computer comprising:
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a central processing unit; and a configurable logic platform connected to the central processing unit, the configurable logic platform comprising; a physical interconnect for connecting the configurable logic platform to the central processing unit; a first reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the first reconfigurable logic region; a second reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the second reconfigurable logic region; a configuration port for applying the configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the configuration data corresponding to the second reconfigurable logic region; a control plane function accessible via transactions of the physical interconnect, the control plane function in communication with the configuration port, the control plane function providing restricted access to the configuration port from the physical interconnect; a first data plane function accessible via transactions of the physical interconnect, the first data plane function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect; a second data plane function accessible via transactions of the physical interconnect, the second data plane function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect; and arbitration logic configured to apportion bandwidth of the physical interconnect among at least the first data plane function and the second data plane function. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit comprising:
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a physical interconnect for connecting the integrated circuit to a processor; a first reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the first reconfigurable logic region; a second reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the second reconfigurable logic region; a configuration port for applying the configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the configuration data corresponding to the second reconfigurable logic region; a control plane function accessible via transactions of the physical interconnect, the control plane function in communication with the configuration port, the control plane function providing restricted access to the configuration port from the physical interconnect; a first data plane function accessible via transactions of the physical interconnect, the first data plane function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect; a second data plane function accessible via transactions of the physical interconnect, the second data plane function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect; and arbitration logic configured to apportion bandwidth of the physical interconnect among at least the first data plane function and the second data plane function. - View Dependent Claims (20)
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Specification