Chip encapsulating method and chip encapsulating structure

• US 10,283,376 B2
• Filed: 04/12/2018
• Issued: 05/07/2019
• Est. Priority Date: 07/03/2017
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Qu, Lianjie, Qiu, Yun, Wang, Dan, Zhao, Hebin
• Primary Examiner(s): Schoenholtz, J. E.
• Application Number:
  US15/951,267
• Publication Number:
  US 20190006195A1
• Time in Patent Office: 390 Days
• Field of Search: None
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11001 Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method.

Claims

1. A chip encapsulating method, comprising:

fixing a plurality of wafers to a first panel level substrate, a wafer comprising a plurality of chips;

forming a re-distribution layer on the wafer for each of the chips;

forming each individual chip and the re-distribution layer connected to the chip by cutting;

fixing the chip and the re-distribution layer connected to the chip to a second panel level substrate; and

encapsulating the chip to form an encapsulating layer.

2. The chip encapsulating method of claim 1, wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate, the re-distribution layer is close to the second panel level substrate;

after the chip is encapsulated, the chip encapsulating method further comprises;

removing the second panel level substrate;

fixing the encapsulating layer to a third panel level substrate, and forming a solder ball on one side of the re-distribution layer.

3. The chip encapsulating method of claim 1, wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate, the re-distribution layer is close to the second panel level substrate;

after the chip is encapsulated, the chip encapsulating method further comprises;

cutting the encapsulating layer, to form each individual chip encapsulating body; and

forming a solder ball for each of the chip encapsulating body.

4. The chip encapsulating method of claim 1, wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate, the re-distribution layer is away from the second panel level substrate;

after the chip is encapsulated, the chip encapsulating method further comprises;

decapsulating the encapsulating layer, to expose a contact portion of the re-distribution layer contacting a solder ball; and

forming the solder ball.

5. The chip encapsulating method of claim 1, wherein after the re-distribution layer is formed and before forming each individual chip and the re-distribution layer connected to the chip by cutting, the method further comprises:

removing the first panel level substrate.

6. The chip encapsulating method of claim 1, wherein a shape of the wafer is a regular polygon;

and

a plurality of the wafers is seamlessly arranged on the first panel level substrate.

7. The chip encapsulating method of claim 6, wherein the wafer has a rectangular or regular hexagon shape.

8. The chip encapsulating method of claim 1, wherein the second panel level substrate is a tempered glass substrate.

9. The chip encapsulating method of claim 1, wherein the first panel level substrate and the second panel level substrate have an identical size.

10. The chip encapsulating method of claim 2, wherein the first panel level substrate and the second panel level substrate have an identical size.

11. The chip encapsulating method of claim 3, wherein the first panel level substrate and the second panel level substrate have an identical size.

12. The chip encapsulating method of claim 4, wherein the first panel level substrate and the second panel level substrate have an identical size.

13. The chip encapsulating method of claim 9, wherein the third panel level substrate and the first panel level substrate, the second panel level substrate have an identical size when the encapsulating layer is fixed to the third panel level substrate.

14. The chip encapsulating method of claim 10, wherein the third panel level substrate and the first panel level substrate, the second panel level substrate have an identical size when the encapsulating layer is fixed to the third panel level substrate.

15. The chip encapsulating method of claim 11, wherein the third panel level substrate and the first panel level substrate, the second panel level substrate have an identical size when the encapsulating layer is fixed to the third panel level substrate.

16. A chip encapsulating structure, comprising:

a plurality of wafers fixed to a first panel level substrate, a wafer comprising a plurality of chips;

a re-distribution layer for each of the chips formed on the wafer;

the plurality of chips being individual chips having the re-distribution layer connected to the chips; and

the chip and the re-distribution layer connected to the chip being fixed to a second panel level substrate;

wherein a shape of the wafer is a regular polygon; and

a plurality of the wafers are seamlessly arranged on the first panel level substrate.

17. The chip encapsulating structure of claim 16, wherein the wafer has a rectangular or regular hexagon shape.

18. The chip encapsulating structure of claim 16, wherein the first panel level substrate and the second panel level substrate have an identical size.