Method for ascertaining an internal resistance of an electrical energy accumulator

• US 10,288,695 B2
• Filed: 07/06/2015
• Issued: 05/14/2019
• Est. Priority Date: 08/27/2014
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Stolczenberger, Robert, Varadi, Ferenc, Barany, Gabor
• Primary Examiner(s): Dalbo, Michael J
• Application Number:
  US15/506,541
• Publication Number:
  US 20170254860A1
• Time in Patent Office: 1,408 Days
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: G01R 31/3842 combining voltage and current measurements
• CPC Class Codes: G01R 31/389 Measuring internal impedance, internal conductance or related variables
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A method is described for ascertaining an internal resistance of an electrical energy accumulator. For this purpose, an analog voltage signal and an analog current signal are subjected to an analog to digital conversion and subsequently to band-pass filtering in order to obtain filtered voltage values and filtered current values. These are then checked with regard to different calculation prerequisites, whereupon a zero-phase resistance is calculated. Then, the calculated zero-phase resistance is supplied as internal resistance.

Claims

1. A method for ascertaining an internal resistance of an electrical energy accumulator, the method comprising:

performing an analog to digital conversion of an analog voltage signal and an analog current signal of the electrical energy accumulator in order to obtain digital voltage values and digital current values;

filtering the digital voltage values and the digital current values through a band-pass filter around a zero-phase frequency in order to obtain filtered voltage values and filtered current values,

checking whether the following calculation prerequisites are satisfied;

a first calculation prerequisite in which the band-pass filter is initialized,

a second calculation prerequisite in which a peak current value together with an associated instant of the peak current value is ascertained from the filtered current values;

a third calculation prerequisite in which an amount of the peak current value is greater than an amount of a threshold current value, the amount of the threshold current value being greater than an amount of a minimum threshold current value by which a zero-phase resistance with a predefined maximum deviation from an actual internal resistance is able to be calculated;

a fourth calculation prerequisite in which the filtered voltage value at the previously ascertained instant is a peak voltage value; and

a fifth calculation prerequisite in which the peak current value and the peak voltage value have the same algebraic sign;

checking the calculation prerequisites on an one after the other basis, wherein the first calculation prerequisite is additionally able to be checked at any other arbitrary point during the checking step;

ending the method if one of the calculation prerequisites is not satisfied;

calculating the zero-phase resistance from the peak voltage value and the peak current value if the method was not yet ended previously; and

providing the zero-phase resistance as an internal resistance of the electrical energy accumulator to be determined if the method was not yet ended previously.

2. The method as recited in claim 1, further comprising:

checking a validity of the digital voltage values and the digital current values, the digital voltage values and the digital current values being considered valid if the performing of the analog to digital conversion was carried out successfully, and

ending the method in case of an invalid digital voltage value or an invalid digital current value, wherein the step of checking the validity is carried out after the step of performing the analog to digital conversion and prior to method step a and prior to the step of providing the zero-phase resistance.

3. The method as recited in claim 1, wherein at least one of the peak current value and the peak voltage value is ascertained with the aid of an 3-element FIFO principle.

4. The method as recited in claim 1, further comprising:

checking a plausibility of the calculated zero-phase resistance, wherein the calculated zero-phase resistance is checked to be plausible if the calculated zero-phase resistance lies between a theoretical minimum limit value and a theoretical maximum limit value; and

ending the method in case of an implausible zero-phase resistance, wherein the step of checking the plausibility is carried out between the step of calculating the zero-phase resistance and the step of providing the zero-phase resistance.

5. The method as recited in claim 1, wherein the calculation of the zero-phase resistance includes calculating a quotient from the peak voltage value and the peak current value.

6. The method as recited in claim 5, further comprising:

performing a low-pass filtering of the calculated zero-phase resistance with the aid of a PT1 element, wherein the low-pass filtering is carried out between the step of calculating the zero-phase resistance and the step of providing the zero-phase resistance.

7. The method as recited in claim 1, wherein the calculation of the zero-phase resistance includes calculating a quotient from a root mean square of the voltage peak values and a root mean square of the peak current values.