Accelerated erasure coding system and method

  • US 10,291,259 B2
  • Filed: 05/10/2018
  • Issued: 05/14/2019
  • Est. Priority Date: 12/30/2011
  • Status: Active Grant
First Claim
Patent Images

1. A system adapted to use accelerated error-correcting code (ECC) processing to improve the storage and retrieval of digital data distributed across a plurality of drives, comprising:

  • at least one processor comprising at least one single-instruction-multiple-data (SIMD) central processing unit (CPU) core that executes SIMD instructions and loads original data from a main memory and stores check data to the main memory, the SIMD CPU core comprising at least 16 vector registers, each of the vector registers storing at least 16 bytes;

    at least one system drive comprising at least one non-volatile storage medium that stores the SIMD instructions;

    a plurality of data drives each comprising at least one non-volatile storage medium that stores at least one block of the original data, the at least one block comprising at least 512 bytes;

    more than two check drives each comprising at least one non-volatile storage medium that stores at least one block of the check data;

    at least one first input/output (I/O) controller that receives the at least one block of the original data from a transmitter and that stores the at least one block of the original data to the main memory; and

    at least one second input/output (I/O) controller that stores the at least one block of the check data from the main memory to the check drives, wherein the processor, the SIMD instructions, the non-volatile storage medium, and the at least one second I/O controller are configured to implement an erasure coding system comprising;

    a data matrix comprising at least one vector and comprising a plurality of rows of at least one block of the original data in the main memory, each of the rows being stored on a different one of the data drives;

    a check matrix comprising more than two rows of the at least one block of the check data in the main memory, each of the rows being stored on a different one of the check drives, one of the rows comprising a parity row comprising the Galois Field (GF) summation of all of the rows of the data matrix; and

    a thread that executes on the SIMD CPU core and comprising;

    at least one parallel multiplier that multiplies the at least one vector of the data matrix by a single factor to compute parallel multiplier results comprising at least one vector;

    at least one parallel adder that adds the at least one vector of the parallel multiplier results and computes a running total; and

    a sequencer wherein the sequencer orders load operations of the original data into at least one of the vector registers and computes the check data with the parallel multiplier and the parallel adder, and stores the computed check data from the vector registers to the main memory.

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